IP Design Engineer (AI)

TL;DR

IP Design Engineer (AI): Designing and implementing RTL for AI acceleration IPs and SoC components with an accent on architectural definition and cross-functional hardware execution. Focus on resolving complex RTL issues, optimizing hardware performance, and participating in the full silicon lifecycle from design to bring-up.

Location: Onsite in Seongnam, South Korea

Company

hirify.global is an AI semiconductor company developing high-performance hardware accelerators for artificial intelligence applications.

What you will do

• Define and design architecture and RTL for AI acceleration IPs and core SoC components.
• Collaborate with verification, integration, and software teams to ensure seamless system functionality.
• Partner with DSP engineers to optimize hardware implementations of specialized algorithms.
• Participate in silicon bring-up and perform hardware debugging to validate performance.
• Utilize quality flows including Lint, CDC, DFT, and Synthesis to ensure design reliability.

Requirements

• 3+ years of professional experience in RTL design using SystemVerilog or Verilog.
• Proven track record covering the full design lifecycle from architecture to RTL implementation.
• Proficiency in logic simulation and debugging tools such as VCS or Xcelium.
• Strong understanding of quality toolchains including Lint, CDC, DFT, and Synthesis.
• Ability to work onsite in the R-TOWER office in Seongnam.

Nice to have

• Experience in designing floating-point units and optimized buffer structures.
• Knowledge of MMU architectures and ARM MMU integration.
• Understanding of AMBA-BUS and high-performance interconnect protocols.
• Experience in power analysis and RTL-level optimization.

Hiring process

• Document screening followed by an online interview.
• On-site technical and culture-fit interviews.
• Final offer negotiation and contract signing.