IP Design Engineer (AI)

Location: On-site in Seongnam, Gyeonggi-do, South Korea

Company

hirify.global develops AI acceleration hardware and SoC technologies.

What you will do

• Define architectures and implement RTL for AI acceleration IPs and core SoC components.
• Collaborate with verification, SoC integration, software, and DSP engineering teams.
• Optimize hardware implementations of specialized algorithms.
• Participate in silicon bring-up and hardware debugging to validate IP performance.
• Contribute across the full silicon lifecycle, from architecture definition through implementation and validation.

Requirements

• 3+ years of experience in RTL design using SystemVerilog or Verilog.
• Experience covering the full design lifecycle from architecture definition to final RTL implementation.
• Proficiency with logic simulation tools such as VCS or Xcelium and complex RTL debugging.
• Experience with industry-standard quality flows, including Lint, CDC, DFT, and synthesis.
• Ability to work on-site in Seongnam, South Korea.

Nice to have

• Experience designing floating-point arithmetic units and optimized buffer structures.
• Understanding of MMU architectures and ARM MMU use in IP design.
• Knowledge of AMBA and other high-performance interconnect protocols.
• Experience estimating and optimizing RTL-level power consumption.

Culture & Benefits

• Cross-functional collaboration across hardware, verification, SoC integration, software, and DSP engineering.
• On-site work environment at the hirify.global office in Seongnam.

Hiring process

• Application screening, online interview, on-site interview, culture-fit interview, offer discussion, and final selection.
• The process and schedule may vary by role and will be communicated individually by email.