Physical Design Engineer - Backend (Semiconductor)

Location: On-site in Seongnam, Gyeonggi-do, South Korea

Company

hirify.global develops semiconductor hardware products.

What you will do

• Implement physical design flows from RTL to GDS to optimize power, performance, and area.
• Perform floorplanning, power planning, hard-macro placement, block partitioning, placement, clock-tree synthesis, and routing.
• Optimize H-tree and clock-mesh implementations while improving turnaround time and design quality.
• Identify and resolve DRC, DFM, LVS, PERC, static and dynamic IR-drop, and electromigration issues.
• Deliver GDS and propose architectural changes that improve physical design QoR.
• Support DSPs and contractors in completing physical-design work within target turnaround times.

Requirements

• Bachelor’s degree or higher in Electrical Engineering, or equivalent practical experience.
• At least 8 years of experience with EDA tool workflows in a semiconductor environment.
• Experience with physical-design processes and tools for automating RTL-to-GDS workflows.
• Proficiency in Tcl, Perl, or Python for workflow automation and data visualization.
• Strong understanding of the relationship between die and package.
• Experience leading physical-design activities, extracting design parameters, summarizing QoR, and analyzing trends.

Culture & Benefits

• On-site work at the R-TOWER location in Seongnam.
• Interview process includes document screening, online interview, on-site interview, culture-fit interview, compensation discussion, and final offer.
• The process and schedule may vary by role and circumstances.

Hiring process

• Document screening.
• Online interview, on-site interview, and culture-fit interview.
• Compensation discussion followed by the final hiring decision.