Physical Design Engineer (Embedded_IoT_Dev)

TL;DR

Physical Design Engineer (Embedded_IoT_Dev): Implementing and optimizing physical design (RTL to GDS) for AI semiconductor hardware with an accent on PPA and QoR. Focus on floorplanning, power planning, timing closure, and resolving complex DRC/DFM and IR-drop violations.

Location: Must be based in Seongnam, South Korea

Company

hirify.global is an AI semiconductor company focused on developing high-performance hardware solutions for AI applications.

What you will do

• Implement physical design (RTL to GDS) to achieve optimal PPA metrics.
• Manage floorplanning, power planning, and hard-macro placement.
• Perform place, CTS, and routing optimizations including H-tree and clock-mesh.
• Debug and resolve DRC/DFM, static/dynamic IR-drop, and EM violations.
• Propose architectural improvements to enhance design quality from a physical standpoint.
• Support design teams and manage contractors to meet target turnaround times.

Requirements

• Bachelor’s or higher degree in Electrical Engineering or related field.
• Minimum of 8 years experience with EDA tool workflows in a semiconductor environment.
• Proficiency in scripting languages such as Tcl, Perl, or Python for automation.
• Strong understanding of the relationship between die and package.
• Proven track record in physical design leadership.

Hiring process

• Application screening
• Online interview
• On-site interview
• Culture-fit interview
• Offer negotiation