Lead Design Engineer (ASIC)

TL;DR

Lead Design Engineer (ASIC): Performing physical design implementation for high-speed, low-power projects with an accent on floorplanning, timing closure, and signoff verification. Focus on leading next-generation design methodologies, flow development, and ensuring successful tapeouts through close collaboration with RTL teams.

Location: Onsite in Seoul, South Korea

Company

hirify.global is a global leader in electronic design innovation, providing software and hardware to enable the creation of the world's most advanced integrated circuits and systems.

What you will do

• Execute full physical design implementation including floorplanning and power grid design.
• Conduct place and route, clock tree synthesis, and timing closure.
• Perform signoff tasks including physical verification (DRC/LVS/Antenna) and EM/IR analysis.
• Develop and implement next-generation physical design methodologies and flows.
• Collaborate with RTL design teams to ensure high-quality design tapeouts.

Requirements

• 5+ years of experience in ASIC design flow and hierarchical physical design strategies.
• Solid knowledge of low power design, DFT, and static timing analysis.
• Experience with advanced deep sub-micron technology nodes.
• Proven ability to work independently and handle hands-on design testing and characterization.
• English proficiency required for professional communication.

Culture & Benefits

• Opportunity to work on complex, high-speed designs at cutting-edge technology nodes.
• Role within a global company focused on solving difficult technological challenges.
• Collaborative team environment with emphasis on technical leadership and innovation.