Design Engineer (ASIC)

Location: Fort Collins, Colorado, USA — 4380 Ziegler Road

Company

hirify.global develops custom CMOS ASICs for AI, cellular, networking, computing, and storage products.

What you will do

• Contribute to the physical implementation of large-scale, multi-hundred-million-gate ASICs.
• Support floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification including DRC/LVS.
• Collaborate on block-level integration, timing analysis, design signoff, and technical design reviews.
• Use commercial and in-house EDA tools for implementation and verification.
• Improve design flows, automation, and deep-submicron methodologies.
• Perform power planning, IR/EM checks, post-route optimization, and contribute across the ASIC cycle from RTL to GDSII and silicon bring-up.

Requirements

• Bachelor’s or master’s degree in Electrical or Electronics Engineering.
• Solid understanding of VLSI design, CMOS logic, and digital circuit fundamentals.
• Familiarity with ASIC physical design, including placement, routing, and timing.
• Proficiency in UNIX/Linux environments and working knowledge of TCL.
• Strong analytical, debugging, communication, collaboration, and problem-solving abilities.
• Ability to work with cross-functional and global engineering teams.

Nice to have

• Familiarity with Python or Perl.
• Exposure to Cadence Innovus, Synopsys ICC2, or PrimeTime.

Culture & Benefits

• Work in a fast-paced R&D environment with close collaboration across disciplines.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Discretionary annual bonus and eligibility for new-hire and annual equity awards.
• Paid holidays, sick leave, vacation, family leave, and other applicable leaves of absence.