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2 дня назад

Staff / Senior Staff Physical Design Engineer (ASIC)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US/Taiwan
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Staff / Senior Staff Physical Design Engineer (ASIC): Driving full-chip and block-level physical implementation from netlist to GDSII with an accent on timing, power, area, and tapeout quality. Focus on timing closure across PVT corners, physical verification signoff, ECO fixes, macro integration, and automation of physical design flows with Python and TCL.

Location: Taiwan; Taipei/Hsinchu

Company

hirify.global is a semiconductor startup building high-performance and energy-efficient graphics processors for immersive content creation and consumption.

What you will do

  • Own the end-to-end physical design flow from synthesis support and floorplanning through placement, CTS, routing, and signoff.
  • Drive setup and hold timing closure across multiple PVT corners using advanced STA methodologies, including OCV and POCV.
  • Debug DRC, LVS, EM, and IR issues and deliver clean physical verification signoff.
  • Optimize designs for power, performance, and area while integrating SRAM, IO, and analog hard macros.
  • Manage ECO flows, GLS, SDF generation, and timing-related debugging.
  • Develop physical design automation scripts in Python and TCL and collaborate with RTL, architecture, verification, foundry, and vendor teams through tapeout.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering or a related field.
  • 8–12 years of ASIC physical design experience, including full-chip or large-block implementation and tapeouts.
  • Strong expertise in floorplanning, power planning, placement, CTS, routing, physical verification, STA, and timing closure.
  • Hands-on experience with Synopsys ICC2, Cadence Innovus, Synopsys PrimeTime, and Mentor Calibre.
  • Experience with advanced semiconductor nodes, preferably 7nm and below.
  • Strong debugging and problem-solving skills.

Nice to have

  • Experience with low-power design techniques such as UPF or CPF.
  • Knowledge of EMIR analysis tools such as Ansys RedHawk-SC and familiarity with multi-voltage designs and power domains.
  • Experience with high-speed interfaces or complex CPU, GPU, or AI SoCs.
  • Exposure to GLS and timing-related silicon debug.
  • Additional Python and TCL scripting expertise.

Culture & Benefits

  • Work in a first-principles semiconductor startup environment focused on reducing barriers to immersive content creation and consumption.
  • Collaborate in a culture built around fearless experimentation, adaptability, and selfless knowledge sharing.
  • Join an inclusive workplace centered on professionalism, integrity, and respect.

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