R&D Engineer IC Design (SystemVerilog)

Location: San Jose, California, USA

Annual base salary: $108,000–$172,800, plus discretionary annual bonus and equity eligibility.

Company

hirify.global develops semiconductor and networking technologies.

What you will do

• Verify complex switch designs at block and chip level.
• Create SystemVerilog-based verification environments, including testbenches, checkers, and transactors.
• Create and execute testplans for RTL and gate-simulation designs.
• Develop ATE testing vectors for silicon validation.
• Create C-based diagnostic tests for execution on actual silicon.

Requirements

• Master’s degree in Electrical and Electronic Engineering, Computer Science, or an equivalent field.
• At least 6 years of experience in design verification.
• Strong knowledge and hands-on experience with verification methods, tools, and environments.
• Strong programming skills in SystemVerilog and scripting languages.
• Onsite work in San Jose, California, USA.

Nice to have

• Knowledge and experience with UVM methodology.
• Knowledge of networking and switching concepts.

Culture & Benefits

• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program and Employee Assistance Program.
• Company-paid holidays, paid sick leave, and vacation time.
• Paid family leave and other legally applicable leave programs.
• Eligibility for discretionary annual bonus and equity plans.