Verification Engineer Senior

TL;DR

Verification Engineer Senior (ASIC/FPGA Verification): Building and leading ASIC verification for blocks, subsystems, and SoCs with an accent on coverage-driven verification, formal methods, and performance/power analysis. Focus on architecting scalable SystemVerilog/UVM verification strategies, driving verification closure through simulation and debugging, and mentoring engineers to improve validation quality from pre-silicon to post-silicon learnings.

Location: US, Texas, Austin (Hybrid: split time between on-site at the assigned hirify.global site and off-site)

Salary: $190,610.00–$269,100.00 USD (annual)

Company: hirify.global

hirify.global develops semiconductor and engineering solutions, including custom ASIC and foundry enablement.

What you will do

• Define and implement scalable, reusable verification strategies, test benches, and verification environments for blocks, subsystems, and SoCs, ensuring coverage targets and alignment to microarchitecture specifications.
• Lead verification execution by creating detailed test plans and running technical reviews with design and architecture teams.
• Implement and run simulation models to verify designs and analyze power and performance, identifying and tracking bugs.
• Replicate issues in pre-silicon, determine root causes, debug failures, and implement corrective measures to resolve failing tests.
• Collaborate with SoC/micro-architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural features.
• Continuously enhance verification methodologies and mentor junior engineers to drive verification closure and validation quality.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related STEM with 8+ years of ASIC/FPGA design verification experience, or Master’s degree with 6+ years.
• Strong OOP principles applied in SystemVerilog UVM or other verification methodologies.
• Experience building UVM and/or formal-based verification architectures and methodologies.
• Experience with industry-standard protocols including AMBA AXI/AXI-S/CHI and low-speed protocols such as UART, SPI, I2C/I3C.
• Familiarity with coverage-driven verification, constrained-random testing, and strong debugging skills.

Nice to have

• Graduate/post-graduate degree in a related STEM field.
• Hands-on experience with simulators such as Synopsys VCS and Cadence Xcelium (or equivalent).
• Experience with scripting languages.

Culture & Benefits

• Hybrid work model: split time between on-site at the assigned hirify.global site and off-site.
• Total compensation package includes competitive pay, stock bonuses, and benefits (health, retirement, vacation).
• Opportunity to use advanced verification techniques (coverage-driven verification, formal methods, performance analysis).
• Mentorship and leadership expectations for developing junior engineers.