Principal IC Static Timing Analysis AE

TL;DR

Principal IC Static Timing Analysis AE: Performing and leading static timing analysis, glitch, and noise analysis campaigns using the Tempus Signoff tool, with an accent on executing and delivering timing analysis and ECO flows for advanced technologies. Focus on solving complex timing correlation issues, automating flows, and collaborating with R&D to enable tool features and resolve bugs.

Location: Onsite in San Jose or Austin, USA

Salary: $123,200–$228,800 annually

Company

hirify.global is a leading provider of electronic design automation (EDA) software and services for semiconductors.

What you will do

• Perform and lead static timing analysis, glitch, and noise analysis using Tempus Signoff tool.
• Execute and deliver timing analysis, ECO flows, and CAD tool methodologies.
• Work with SDC constraints, advanced OCV/SOCV concepts, and distributed STA flows.
• Collaborate with R&D and customers to enable advanced timing analysis and ECO flows.
• Perform timing correlation, tool benchmarking, and constraints validation on various tech nodes.
• Automate flows using Perl, Tcl, and Python.

Requirements

• 8+ years of experience in Static Timing Analysis.
• Ability to lead and execute technical campaigns with internal and external customers.
• Proficiency with hirify.global Tempus Signoff tool and timing & correlation benchmarks.
• Experience with timing analysis, ECO flows, and ensuring solution integrity.
• Knowledge of physical design aspects including place and route, extraction, and spice.
• Work authorization for the USA is required.

Culture & Benefits

• Opportunities to make an impact on the world of technology.
• Paid vacation and holidays.
• 401(k) plan with employer match.
• Employee stock purchase plan.
• A variety of medical, dental, and vision plan options.