RTL Synthesis Engineer

TL;DR

RTL Synthesis Engineer: Debugging timing, area, and congestion issues and running formal verification checks between RTL and Gate level netlist. Focus on logic/physical synthesis, DFT flow development, and static timing analysis methodologies for semiconductor product development.

Location: Onsite in San Jose, California, USA

Salary: $120,000–$192,000 annually

Company

hirify.global is a global technology leader designing, developing, and supplying a broad range of semiconductor and infrastructure software solutions.

What you will do

• Debug timing, area, and congestion issues and work with RTL & Physical designers to resolve them.
• Run Formal Verification checks between RTL and Gate level netlist and debug failures.
• Perform RTL Lint and work with designers to create waivers.
• Develop and implement DFT flow.
• Generate Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SOC.
• Analyze inter-block timing and create IO budgets for various partition blocks.

Requirements

• MS in Electrical Engineering or Computer Engineering with 6+ years of experience in Physical design.
• Expert in Logic/Physical Synthesis using advanced optimization techniques.
• Deep knowledge of industry standards in Physical aware synthesis.
• Experience with CDC, RDC, static timing analysis methodologies and relevant tools.
• Expert with developing automation scripts and design flow.
• Solid understanding of design tape-out to foundries and IC Product development supply chain.

Nice to have

• Understanding of Cadence tools (Genus, Joules, Conformal).
• Understanding of Power analysis tools (Redhawk).
• Deep understanding of Signal Integrity and Power Integrity for High Speed designs.

Culture & Benefits

• Competitive and comprehensive benefits package including medical, dental, and vision plans.
• 401(K) participation including company matching.
• Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
• Company paid holidays, paid sick leave, and vacation time.
• Commitment to being an equal opportunity employer.