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3 дня назад

Digital Design Engineer, Principal (AI)

146 850 - 220 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
principal
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR

Principal Digital Design Engineer (AI): Architecting and developing advanced System-on-Chip (SoC) designs for next-generation AI datacenter technologies with an accent on micro-architecture, RTL development, and HW/SW co-design. Focus on delivering complex, high-performance solutions and mastering SoC front-end design flow from timing closure to power optimization.

Location: Santa Clara, CA. This position may require access to technology and/or software subject to U.S. export control laws and regulations. Applicants must be eligible to access export-controlled information. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Salary: $146,850 - $220,000 per annum

Company

hirify.global provides essential semiconductor solutions that form the building blocks of data infrastructure for enterprise, cloud, AI, and carrier architectures.

What you will do

  • Drive micro-architecture and RTL development for AI datacenter technologies.
  • Lead HW/SW co-design efforts for next-generation System-on-Chip (SoC) switch processors.
  • Architect and develop advanced SoC designs, including Ethernet MAC, PCS, and packet processing engines.
  • Partner with architects and verification engineers to design, validate, and optimize timing-critical systems.
  • Master every stage of the SoC front-end design flow, from timing closure to power optimization.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering, or related field with 10–15 years of industry experience, or Master’s/PhD with 5–10 years in digital IC design.
  • Deep practical knowledge of System-on-Chip architecture, including processor cores, memory subsystems, and peripheral interfaces.
  • Extensive experience creating and optimizing Verilog RTL, with expertise in Spyglass for LINT and CDC checks.
  • Skilled in Perl and Python scripting for accelerating design workflows.
  • Track record of delivering production-quality designs on aggressive schedules.
  • In-depth knowledge of IEEE 802.3 Ethernet standards.
  • Work authorization to comply with US export control laws and regulations is required.

Culture & Benefits

  • Comprehensive benefits supporting financial well-being, family support, mental/physical health, and recognition.
  • Employee stock purchase plan with a 2-year look back.
  • Family support programs, robust mental health resources.
  • Recognition and service awards.

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