Senior Staff Digital Design Engineer (Wireline PHYs)

TL;DR

Senior Staff Digital Design Engineer (Wireline PHYs): Architecting and implementing digital control, DSP, and datapath logic for high-performance wireline PHY IP within SoCs and ASICs with an accent on embedded microcontroller integration, bus protocols, and system validation. Focus on driving timing closure, optimizing PHY integration, and supporting post-silicon debug for system-level interactions.

Location: Santa Clara, CA. This position may require access to technology and/or software subject to U.S. export control laws and regulations, requiring applicants to be eligible to access export-controlled information as defined under applicable law. Except for U.S. citizens, lawful permanent residents, or protected individuals, all applicants may be subject to an export license review process prior to employment.

Salary: $124,420 – $186,400 per annum

Company

hirify.global provides semiconductor solutions that are essential building blocks for global data infrastructure across enterprise, cloud, AI, automotive, and carrier architectures.

What you will do

• Architect and implement RTL for digital control, DSP blocks, digital datapath, and adaptation engines of PHY IP for SerDes, Die-to-Die, and Parallel Optics applications.
• Design and verify bus interfaces (APB, AHB, AXI) and register maps for microcontroller communication and firmware control.
• Collaborate closely with system architects and firmware teams to optimize PHY integration into SoC and chiplet environments.
• Drive timing closure and ensure synthesis-friendly RTL targeting system-level constraints and goals.
• Support system bring-up activities, validation planning, and post-silicon debug, focusing on system-level interactions involving digital datapath and DSP logic.
• Mentor junior engineers and contribute to improving design methodologies for PHY system integration.

Requirements

• Master’s degree +7 years or PhD +4 years in Electrical Engineering, Computer Engineering, or related fields.
• Strong RTL design expertise in Verilog/SystemVerilog, with a focus on digital control blocks, DSP, digital datapath, and bus protocols.
• Solid understanding of logic synthesis, static timing analysis (STA), constraints development, and timing closure at block and chip levels.
• Deep knowledge of CDC and RDC design principles.
• Experience integrating PHY digital blocks, including DSP and datapath modules, with embedded microcontrollers.
• Familiarity with scripting for design automation (Python, TCL, Perl).
• Proven problem-solving and debug experience at system level, including post-silicon validation, particularly for DSP and datapath components.

Nice to have

• Understanding of firmware-hardware co-design and system bring-up tools.

Culture & Benefits

• Total compensation package with base, bonus, and equity.
• Health and financial wellbeing benefits, including flexible time off, 401k, a year-end shutdown, floating holidays, and paid time off to volunteer.
• Commitment to fair and authentic hiring practices.

Hiring process

• Candidates are asked not to use AI tools (e.g., transcription apps, real-time answer generators, or note-taking bots) during interviews.
• Usage of such tools during an interview will result in disqualification from the hiring process.