Distinguished Engineer (ASIC)

TL;DR

Distinguished Engineer (ASIC): Designing and implementing complex digital IC / ASIC / SoC solutions for medical imaging devices with an accent on RTL ownership, silicon-level implementation, and PPA tradeoffs. Focus on architecting high-throughput digital datapaths, resolving functional issues, and collaborating cross-functionally to close chip-level requirements.

Location: Butterfly offers a hybrid work model with 2+ days/week in office for most positions. For this role, location depends on qualifications and experience, with options in Burlington, MA or New York City, NY. Highly qualified candidates may be considered for a fully remote role within the United States (specific states apply).

Salary: $240,000 along with bonus, equity, and comprehensive benefits.

Company

hirify.global is a product company leading a digital revolution in medical imaging with proprietary Ultrasound-on-Chip™ technology and AI-enabled software.

What you will do

• Own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation and verification signoff.
• Implement silicon-proven digital architectures, including pipelined datapaths, control logic, state machines, and high-throughput streaming interfaces.
• Architect sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design.
• Collaborate with verification, analog, systems, and packaging/board teams to close chip-level requirements.
• Define and implement hardware–firmware interfaces (register maps, control/status paths, data-plane contracts).

Requirements

• BS/MS/PhD in EE/CE/CS or equivalent practical tapeout experience.
• 8–12+ years in digital IC / ASIC / SoC design with significant hands-on RTL ownership.
• Strong understanding of digital IC implementation at the silicon level, including timing closure implications and power-aware design.
• Proven ability to own complex digital IC subsystems from architecture through tapeout handoff to physical design.
• Strong RTL skills in SystemVerilog/Verilog to implement silicon-proven digital architectures.
• Prior work at advanced technology nodes (28nm or smaller) and experience collaborating with verification teams.

Nice to have

• Experience implementing compute-intensive digital pipelines (e.g., DSP, beamforming, AI, or MAC-heavy/vector datapaths).
• Exposure to medical imaging / ultrasound systems, beamforming pipelines, or sensor data acquisition architectures.
• Experience designing or integrating programmable digital compute blocks (e.g., AI accelerators, MPUs, or eFPGA fabrics).

Culture & Benefits

• Comprehensive health, dental, and vision insurance with HSA contributions.
• Comprehensive Employee Assistance Program.
• 401k plan with company match and Employee Stock Purchase Plan (ESPP).
• Unlimited Paid Time Off + 10 Holiday Days a Year and Parental Leave.
• Competitive salaried compensation and equity opportunities.
• Opportunity to build a revolutionary healthcare product and save millions of lives.