Design Verification Engineer

Location: On-site in Santa Clara, California, United States

Annual salary: $105,650–$149,150 USD

Company

hirify.global is developing configurable interconnect and chassis generators for SoCs and chiplets through its Unified hirify.global Chassis team.

What you will do

• Develop simulation tests, formal properties, reference models, and checkers for interconnect and chassis IP.
• Debug simulation failures and formal counterexamples, distinguish design issues from testbench or assumption errors, and coordinate resolutions with relevant owners.
• Translate specifications into verification plans and checks, review assumptions and coverage gaps, and take scoped features from bring-up through verification closure.
• Participate in architecture and design discussions and contribute reviewed RTL or model changes.
• Build scripts and reusable tools for configuration generation, regression execution, and results analysis across generated designs.
• Use AI-assisted tools for coding, property development, and debugging while reviewing and validating generated work with tests and formal analysis.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 6+ months of work or academic experience.
• Foundational knowledge of digital logic, sequential circuits, and computer architecture, with the ability to read and reason about RTL.
• Programming and algorithmic problem-solving skills demonstrated in C, C++, Python, or an HDL through coursework, research, projects, or internships.
• Experience explaining expected behavior, devising tests, and investigating unexpected results.
• Hands-on use of AI-assisted development tools in coursework, research, or projects, including reviewing and testing generated code.
• hirify.globallectual curiosity, willingness to ask questions and incorporate feedback, a methodical problem-solving approach, and clear cross-disciplinary communication.

Nice to have

• Coursework or project experience with RTL simulation, formal verification, SystemVerilog assertions, or UVM.
• Familiarity with interconnects, cache and memory hierarchies, or AXI, CHI, or PCIe protocols.
• Hands-on projects involving RTL design, FPGA implementation, hardware modeling, or hardware-software co-design.
• Experience with Linux, Git, scripting, and automated build or test flows.
• Experience building AI-assisted workflows for specification analysis, test or property generation, or debugging.

Culture & Benefits

• Full-time college graduate role with learning opportunities through building, testing, code review, and collaboration with experienced engineers.
• Benefits include health coverage, retirement programs, vacation, competitive pay, and stock bonuses.
• The role requires an on-site presence and is not eligible for hirify.global immigration sponsorship.
• hirify.global does not charge recruitment, medical examination, or other fees during the hiring process.