VLSI ASIC Logic Design Engineer (SystemVerilog)

Location: Hybrid, working an average of 2 days per week from an HPE office in Ft. Collins, Colorado; Bloomington, Minnesota; Chippewa Falls, Wisconsin; or Frisco, Texas, United States.

Salary: Base annual salary of USD 115,000–218,000 in Colorado or USD 109,000–251,000 in Minnesota, Texas, and Wisconsin. Variable incentives may also be offered.

Company

hirify.global is an edge-to-cloud technology company developing solutions that connect, protect, analyze, and manage data and applications.

What you will do

• Design VLSI and RTL using SystemVerilog for reliable, cost-effective ASIC prototypes and products.
• Create SystemVerilog Assertions and use formal verification to prove design correctness.
• Write coverage, measure stimulus quality, and analyze coverage gaps.
• Document design intent for verification and firmware teams.
• Analyze system latency and bandwidth trade-offs, identify bottlenecks, and propose solutions.
• Collaborate with VLSI engineers, management, internal partners, and outsourced development partners; mentor less experienced staff.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or an equivalent field.
• 1–6 years of experience in VLSI design, verification, or implementation.
• Strong knowledge of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
• Strong analytical and problem-solving skills.
• Experience designing VLSI components, integrated circuitry, architectures, and algorithms.
• Knowledge of programming and scripting, hardware description languages, EDA, and/or FPGA tools; coursework in VLSI design or concepts.
• Strong written and verbal communication skills; mastery of English and the local language.
• Subject-matter knowledge in the main responsibility areas, with growing breadth and depth of expertise.

Nice to have

• Understanding of the OSI model for layered networking stacks.
• Experience with Ethernet protocols, CPU or GPU systems, and high-speed peripherals.
• Experience with formal verification and design verification using UVM.

Culture & Benefits

• Hybrid work with an average of two office days per week.
• Health and wellbeing benefits supporting physical, financial, and emotional wellbeing.
• Personal and professional development programs supporting career growth and movement across divisions.
• Inclusive workplace committed to accessibility and equal employment opportunity.

Hiring process

• Accommodation requests for disability-related needs during the application or interview process can be submitted through HPE’s secure support form.
• The estimated application period closure is February 1, 2027.