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6 дней назад

Principal Design Verification Engineer (AI Fabric Switches)

185 000 - 240 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Principal Design Verification Engineer (AI Fabric Switches) (SystemVerilog/UVM/C/C++): Developing functional verification for complex ASICs used in server, storage, networking, and AI infrastructure with an accent on hybrid directed and constrained-random verification, coverage, and debugging. Focus on planning verification lifecycles, building test sequences, executing emulation-based validation, and closing coverage for high-quality tape-outs.

Location: San Jose, California, United States; other location: California. Applicants must be authorized to work in the US and able to start immediately.

Base salary: USD 185,000.00–240,000.00 annually, determined by location, experience, and comparable employee compensation.

Company

hirify.global provides rack-scale AI infrastructure through connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and the COSMOS software suite.

What you will do

  • Own the full verification lifecycle for complex ASIC designs, from planning and test development through debugging and coverage closure.
  • Develop and deploy hybrid directed and constrained-random verification techniques.
  • Write test plans and test sequences to generate stimuli and validate design functionality.
  • Identify stimulus and corner-case coverage measures and close coverage holes before tape-out.
  • Collaborate with RTL designers, software teams, and system validation teams to debug failures and execute test plans on emulation platforms.

Requirements

  • Bachelor’s degree in electrical engineering or a related technical field; a Master’s degree is preferred.
  • At least 8 years of experience verifying and validating complex SoCs for server, storage, and networking applications.
  • Full verification lifecycle experience using SystemVerilog, UVM, C, and C++.
  • Experience with directed and constrained-random verification, test planning, stimulus generation, debugging, and coverage closure.
  • Ability to work independently, prioritize multiple tasks, and operate with minimal guidance.
  • Knowledge of industry-standard simulators, revision control systems, and regression systems.
  • Ability to collaborate with RTL designers to debug failures and identify verification gaps.
  • US work authorization and immediate availability are required.

Nice to have

  • Master’s degree in electrical engineering.
  • Perl or Python scripting experience for verification infrastructure automation.
  • Experience with third-party Verification IP and protocols including PCI Express Gen 3+, Ethernet, InfiniBand, DDR4/5, NVMe, or USB.
  • Experience with formal methods, directed-test methodologies, cache verification, or emulation.

Culture & Benefits

  • Work in an environment focused on creativity, innovation, and diverse ideas, backgrounds, and experiences.
  • Applicants from diverse backgrounds, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities, are encouraged to apply.

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