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3 дня назад

Design Verification Engineer (3D NAND)

121 280 - 194 100$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Design Verification Engineer (3D NAND): Building pre-silicon verification environments for advanced 3D NAND designs with an accent on UVM, functional coverage, assertions, and mixed-signal modeling. Focus on developing constrained-random tests, debugging simulation failures, closing coverage, and automating verification workflows.

Location: Rancho Cordova, California, United States; hybrid role requiring reporting to the site 3 days per week

Salary: $121,280–$194,100 per year, plus eligibility for RSU, RCU, and cash bonus programs

Company

hirify.global is a multibillion-dollar memory technology company developing NAND memory and optimized data storage products, combining established technology-company scale with a startup-oriented operating style.

What you will do

  • Create and maintain verification test plans from design specifications.
  • Develop UVM-based directed and constrained-random tests, debug simulation failures, and distinguish design, testbench, and test issues.
  • Define functional coverage models, analyze results, and drive coverage closure.
  • Create and maintain SystemVerilog Assertions for 3D NAND designs and enhance UVM verification environments.
  • Develop mixed-signal full-chip models and verification environments, including analog behavioral models, cell-level testbenches, and mixed-signal netlists.
  • Automate verification workflows, regression execution, results processing, and data collection with scripts and tools.

Requirements

  • Master’s degree with 3+ years of relevant experience, or bachelor’s degree with 5+ years, in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Prior pre-silicon verification experience with memory products is required.
  • Hands-on experience with UVM, SystemVerilog Assertions, and formal property verification.
  • Hands-on mixed-signal verification, modeling, and simulation experience with strong knowledge of digital and analog circuit design.
  • Strong data analysis skills and the ability to communicate technical findings through written reports and presentations.
  • Independent debugging and problem-solving skills, with proficiency in programming or scripting for design and verification automation.
  • Excellent written and verbal communication skills and the ability to collaborate across design, verification, modeling, and cross-functional teams.

Nice to have

  • Memory-industry verification experience, full-chip and regression verification, and code and functional coverage closure.
  • Python, Perl, or shell scripting experience.
  • AI-assisted workflows and commercial simulation, formal, and mixed-signal tools.

Culture & Benefits

  • Hybrid work arrangement with 3 days per week at the Rancho Cordova site.
  • Medical, dental, vision, supplemental life and AD&D insurance.
  • Short- and long-term disability coverage and healthcare and dependent care flexible spending accounts.
  • Company match on eligible 401(k) plan contributions, plus restricted stock, restricted cash, and cash bonus programs.
  • Collaborative, inclusive, customer-inspired, and results-driven work environment.

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