RTL Engineer – Physical AI Solutions

Location: San Jose, California, United States. Shift 1, United States of America.

Salary: $149.1K–$238.2K USD annually for the Bay Area California; incentive opportunities may also be available.

Company

hirify.global develops programmable silicon, FPGA, and adaptive computing technologies for cloud, edge, communications, industrial, automotive, and emerging AI applications.

What you will do

• Design and develop synthesizable Verilog/SystemVerilog RTL for FPGA and programmable hardware supporting Physical AI applications.
• Translate architectural specifications into microarchitecture designs and participate in architecture and design reviews.
• Optimize hardware for performance, area, power, and scalability.
• Define verification strategies, close functional coverage, and debug RTL, simulation, emulation, and silicon-related issues.
• Support synthesis, static timing closure, FPGA implementation, performance analysis, hardware-software integration, and system bring-up.
• Collaborate with architects, verification, software, firmware, and physical design engineers on next-generation AI acceleration technologies.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 3+ years of experience in RTL design and digital logic development.
• Strong expertise in Verilog and/or SystemVerilog.
• Solid understanding of computer architecture, digital design fundamentals, and ASIC/FPGA design methodologies.
• Experience with simulation, debugging, verification tools, and high-performance datapath, control logic, or accelerator architectures.
• Familiarity with synthesis, static timing analysis, and FPGA implementation flows.
• Strong analytical, debugging, problem-solving, communication, and collaboration abilities.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related discipline.
• Experience designing AI, machine learning, vision-processing, signal-processing, networking, or robotics accelerators.
• Knowledge of FPGA architectures, adaptive computing platforms, high-bandwidth memory, NoC, PCIe, Ethernet, CXL, or coherent interconnects.
• Experience with Synopsys, Siemens EDA, or Cadence design environments and hardware/software co-design.
• Familiarity with Python, C/C++, or scripting languages for design automation and validation.
• Experience developing solutions for robotics, industrial automation, autonomous systems, or edge AI applications.

Culture & Benefits

• Regular, full-time employment.
• Work with programmable silicon technologies and engineers solving complex hardware challenges.
• Opportunity to contribute to computing architectures across cloud, edge, and autonomous systems.
• Incentive opportunities may reward individual and company performance.
• Artificial intelligence is used to screen, assess, or select applicants.