ASIC DFT Engineer

Location: San Jose, California, United States; onsite at the San Jose Development Center

Annual base salary: USD 121,900–195,000

Company

hirify.global's ASIC Product Division develops ASIC and SoC designs and related DFT solutions.

What you will do

• Define DFT specifications based on product, customer, DPPM, and testability requirements.
• Implement SoC DFT features including Scan, MBIST, TAP, LBIST, IO, and SerDes DFT integration.
• Generate, verify, and debug test vectors before tape release and validate them on ATE during silicon bring-up.
• Collaborate with STA, physical design, integration, test engineering, manufacturing, customers, and other DFT stakeholders.
• Support silicon failure analysis, diagnostics, yield improvement, and debugging of customer-returned parts.
• Automate DFT and test-vector generation flows and develop solutions for testability challenges in 3nm-and-beyond designs.

Requirements

• Strong DFT experience in areas such as IO and analog DFT, ATPG, Scan, and BIST.
• Experience with scan insertion and scan compression using tools such as DFT Compiler or Mentor TestKompress.
• Experience designing and debugging Logic BIST, and inserting and verifying Memory BIST for SRAM, CAM, and eDRAM.
• Experience generating, simulating, and debugging ATPG vectors using tools such as TetraMax or Fastscan.
• Experience with Verilog coding, testbench generation, and simulation.
• Basic coding or scripting skills in TCL, Perl, Python, C++, or Verilog.
• Solid knowledge of analog and digital circuit design, device physics, silicon processing, logical and physical synthesis, and transistor reliability principles.
• Ability to work in a multidisciplinary, cross-department environment with strong problem-solving, debugging, root-cause analysis, and communication skills.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, plus 10+ years of experience.

Nice to have

• Experience working on ATE.

Culture & Benefits

• Full-time position with collaboration across globally located customer, physical design, test engineering, and manufacturing teams.
• Eligible for a discretionary annual bonus and new-hire and annual equity awards, subject to applicable plans and agreements.
• Benefits include medical, dental and vision plans, 401(k) with company matching, ESPP, EAP, paid holidays, paid sick leave, vacation, and applicable paid family and other leave.
• Equal opportunity employment is provided in accordance with applicable federal, state, and local laws.

Hiring process

• First-time applicants must create a candidate login account before applying; existing candidates must sign in before applying.
• Applicants located outside the USA should provide a home address for future correspondence.