Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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$134к-201к/год
$160к$170кмедиана$190к
По похожим ролям (50) ~ $170к/год
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У роли четкие задачи senior-уровня в разработке передовых чипов для оптических сетей и AI-инфраструктуры: от внедрения DFT до sign-off и отладки кремния. Требования экспортного контроля могут ограничить круг тех, кто сможет получить доступ к проекту.
Ограничение по доступу
Передовые чипы
Четкая зона ответственности
Акции и бонусы
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Sr Staff Engineer-DFT (ASIC/DFT): Defining DFT architecture and implementation for advanced-node Optical DSP ASICs with an accent on hierarchical DFT, ATPG coverage, compression, timing, and silicon debug. Focus on integrating IP-level DFT, leading sign-off and handoff to PD/ATE, diagnosing silicon failures, and improving methodology and automation.
Location: Santa Clara, California, United States
Expected base pay: $134,390–$201,300 per annum
Company
hirify.global develops semiconductor solutions and advanced ASICs for enterprise, cloud, AI infrastructure, hyperscale data centers, and optical networking.
What you will do
Define DFT architecture and implementation for chip blocks, including hierarchical DFT, test modes, and clocking.
Plan, partition, and integrate IP-level DFT for SerDes, PLLs, memories, and third-party IP.
Drive ATPG coverage, test-time, pattern-count, compression, and test-power targets.
Lead DFT sign-off across DRC, simulation, timing, equivalence, and handoff to physical design and ATE.
Debug silicon through failure isolation, diagnosis, and yield learning with product and test engineering.
Mentor junior engineers, coordinate cross-functionally, and improve methodology and automation.
Requirements
BS in EE/CE with 8+ years or MS in EE/CE with 5+ years of DFT experience on complex SoCs.
Multiple tape-outs and silicon bring-ups.
Deep expertise in scan, compression, ATPG fault models, MBIST/repair, JTAG, and at-speed testing.
Strong DFT timing and STA knowledge.
Proven independent problem-solving and mentoring skills.
Must be eligible to access export-controlled technology and software under U.S. export control laws; an export license review may apply.
Nice to have
Experience with advanced process nodes, preferably 7nm and below.
Experience with high-speed SerDes/DSP products.
Culture & Benefits
Full-time role within a global, multi-site engineering organization.
Eligibility for bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
Employee stock purchase plan with a two-year lookback.
Family support programs, mental and physical health resources, recognition programs, and service awards.
AI tools, transcription apps, automated note-taking bots, and real-time answer generators are prohibited during interviews; unauthorized use results in disqualification.
Hiring process
Applicants requiring reasonable accommodation during selection may contact the hirify.global HR Helpdesk.
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