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4 дня назад

Senior Principal Engineer-DFT (ASIC/DFT)

182 360 - 273 200$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Principal Engineer-DFT (ASIC/DFT): Architecting and implementing DFT and test methodologies for complex mixed-signal ASICs used in hyperscale data centers, enterprise systems, and AI infrastructure with an accent on DFT architecture, validation, STA, pattern generation, and post-silicon debug. Focus on leading multi-generation DFT execution, mentoring a full engineering team, and enhancing DFT tools and methodologies for advanced semiconductor designs.

Location: Santa Clara, CA, United States

Expected base pay: $182,360–$273,200 per annum

Company

hirify.global develops semiconductor solutions and advanced ASICs for enterprise, cloud, AI infrastructure, hyperscale data centers, and optical networking.

What you will do

  • Architect, lead, and implement DFT and test methodologies for complex mixed-signal SoCs across multiple generations.
  • Define DFT/DFX architectures and implement SCAN, MBIST, IP-DFT, STA, validation, pattern generation, and related features.
  • Lead post-silicon bring-up and debug for designs and IPs in custom and compute domains.
  • Mentor and guide a full team of DFT engineers across multiple designs.
  • Define and enhance DFT methodologies and tools, including benchmarking and new approaches.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 15+ years of related professional experience; or a Master’s degree and/or PhD with 13+ years of experience.
  • Hands-on experience across DFT execution stages, including SCAN, MBIST, validation, STA, IP-DFX, post-silicon bring-up, and debug.
  • Thorough knowledge of DFT and test architecture solutions, including participation in the architecture definition of at least two designs.
  • Strong fundamentals in digital circuit design and logic design.
  • Experience with DFT flows and methodologies and Cadence, Mentor, and Synopsys toolsets, including Genus, Modus, NCSim, DC, Tessent, Spyglass, and Tmax.

Nice to have

  • Prior ASIC design experience.
  • Scripting skills with Python, Perl, Tcl, and C-Shell.

Culture & Benefits

  • Full-time role within a global, multi-site engineering organization.
  • Eligible for bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
  • Benefits include an employee stock purchase plan, family support programs, mental health resources, and recognition awards.
  • Applicants must be eligible to access export-controlled technology and software under U.S. export control laws; candidates may be subject to an export license review before employment.
  • Reasonable accommodation is available during the selection process.

Hiring process

  • AI tools, transcription apps, real-time answer generators, and automated note-taking bots are prohibited during interviews; unauthorized use results in disqualification.

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