Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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$142к-173к/год
$190к$200кмедиана$220к
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Чётко описанная позиция в области GPU DFT в крупной полупроводниковой компании даёт возможность заниматься профильной и значимой работой, хотя задачи охватывают несколько этапов проектирования и верификации.
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Ниже рынкаШирокий круг задачРазработка GPUПонятные требования
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Senior DFT Design Engineer (GPU): Designing and validating scan/ATPG DFT features, RTL graphics IP, and GPU blocks for high-performance visual computing with an accent on automation, simulation, timing analysis, and silicon enablement. Focus on developing test patterns, debugging post-silicon ATPG content, optimizing designs for power, performance, area, and timing, and supporting SoC integration.
Location: Hybrid work model based at an hirify.global site in Folsom, California; additional locations include Hillsboro, Oregon; Santa Clara, California; and Phoenix, Arizona, United States.
Annual salary: $141,910–$172,860 USD.
Company
hirify.global designs and manufactures silicon products and develops technologies for data-intensive workloads, including next-generation graphics engines and visual computing solutions.
What you will do
Design, validate, automate, and perform timing analysis for Scan and ATPG DFT features.
Contribute to trace and pattern generation, post-silicon enablement, debug support, and ATPG content analysis.
Develop RTL, logic designs, simulations, and GPU IP blocks covering graphics, compute, display, and media.
Define block architecture and microarchitecture features and optimize logic for power, performance, area, timing, and design integrity.
Support SoC customers with high-quality GPU block integration.
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related STEM field with 4+ years of industry experience; or a master’s degree with 3+ years; or a PhD with 1+ years.
Experience with Scan, ATPG, or other DFT features.
Experience in SoC or IP DFT design, integration, or verification.
Experience with EDA tools such as Siemens Tessent, ATPG tools, Synopsys VCS, or other simulation and debug tools.
Nice to have
Silicon enablement debug or test pattern development experience.
Design automation skills and proficiency in programming or scripting languages.
Experience with structural design flows, including timing, routing, placement, or clocking analysis.
Knowledge of high-volume manufacturing requirements and test flows.
Experience with 3D, media, and display graphics pipelines.
SoC architecture experience.
Culture & Benefits
Hybrid work model splitting time between the assigned hirify.global site and off-site work.
Competitive annual compensation, stock bonuses, health benefits, retirement benefits, and vacation.
Full-time experienced-hire position on Shift 1 in the United States.
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