Назад
Company hidden
56 минут назад

Senior DFT Design Engineer (GPU)

141 910 - 172 860$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Senior DFT Design Engineer (GPU): Designing and validating scan/ATPG DFT features, RTL graphics IP, and GPU blocks for high-performance visual computing with an accent on automation, simulation, timing analysis, and silicon enablement. Focus on developing test patterns, debugging post-silicon ATPG content, optimizing designs for power, performance, area, and timing, and supporting SoC integration.

Location: Hybrid work model based at an hirify.global site in Folsom, California; additional locations include Hillsboro, Oregon; Santa Clara, California; and Phoenix, Arizona, United States.

Annual salary: $141,910–$172,860 USD.

Company

hirify.global designs and manufactures silicon products and develops technologies for data-intensive workloads, including next-generation graphics engines and visual computing solutions.

What you will do

  • Design, validate, automate, and perform timing analysis for Scan and ATPG DFT features.
  • Contribute to trace and pattern generation, post-silicon enablement, debug support, and ATPG content analysis.
  • Develop RTL, logic designs, simulations, and GPU IP blocks covering graphics, compute, display, and media.
  • Define block architecture and microarchitecture features and optimize logic for power, performance, area, timing, and design integrity.
  • Drive unit-level verification, review verification plans, resolve failing RTL tests, and ensure feature correctness.
  • Support SoC customers with high-quality GPU block integration.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related STEM field with 4+ years of industry experience; or a master’s degree with 3+ years; or a PhD with 1+ years.
  • Experience with Scan, ATPG, or other DFT features.
  • Experience in SoC or IP DFT design, integration, or verification.
  • Experience with EDA tools such as Siemens Tessent, ATPG tools, Synopsys VCS, or other simulation and debug tools.

Nice to have

  • Silicon enablement debug or test pattern development experience.
  • Design automation skills and proficiency in programming or scripting languages.
  • Experience with structural design flows, including timing, routing, placement, or clocking analysis.
  • Knowledge of high-volume manufacturing requirements and test flows.
  • Experience with 3D, media, and display graphics pipelines.
  • SoC architecture experience.

Culture & Benefits

  • Hybrid work model splitting time between the assigned hirify.global site and off-site work.
  • Competitive annual compensation, stock bonuses, health benefits, retirement benefits, and vacation.
  • Full-time experienced-hire position on Shift 1 in the United States.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →