Senior Lead Design Engineer (FPGA)

Location: San Jose, California, United States. Shift 1.

Salary: $231,500–$330,000 USD annually for the Bay Area, California; incentive opportunities may also apply.

Company

hirify.global develops programmable technology, including FPGA and programmable SoC solutions for data center, networking, AI, and edge applications.

What you will do

• Lead architecture, microarchitecture, and RTL development for complex FPGA, programmable SoC, and infrastructure-class subsystems.
• Define requirements, interfaces, specifications, and implementation plans across hardware, firmware, software, validation, and product teams.
• Own critical blocks through RTL implementation, synthesis, integration, verification support, timing closure, bring-up, performance characterization, and issue resolution.
• Drive tradeoffs involving performance, power, area, latency, bandwidth, reliability, scalability, cost, and schedule.
• Establish reusable design IP, coding standards, automation, and quality methodologies.
• Provide technical mentorship, lead cross-functional issue resolution, and influence roadmaps, tools, IP, and technology choices.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline, with 15+ years of relevant experience in FPGA, ASIC, SoC, or semiconductor product development; an advanced degree is preferred.
• Technical leadership delivering complex digital subsystems or products from system architecture and microarchitecture through RTL, verification, integration, implementation, and post-silicon or hardware validation.
• Hands-on expertise in Verilog and/or SystemVerilog RTL design, synthesis, lint, CDC/RDC, formal or equivalence checking, timing constraints, and implementation-aware design.
• Experience with high-performance digital architectures such as networking or packet-processing datapaths, acceleration engines, PCIe/CXL, Ethernet, DDR/HBM memory subsystems, high-speed interfaces, or on-chip interconnect.
• Strong understanding of performance, power, area, timing, bandwidth, latency, congestion, and reliability tradeoffs.
• Experience leading execution across multiple functional blocks or chip-level integration, including planning, risk management, schedule alignment, and technical prioritization.
• Ability to collaborate and influence across architecture, RTL, verification, physical design, CAD, firmware/software, system validation, and product engineering organizations.
• Strong written and verbal communication skills.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Experience with FPGA architecture, programmable-logic devices, configurable interconnect, SmartNICs, IPUs, SoCs, or data-center acceleration platforms.
• Experience building or maintaining reusable design IP across multiple products, programs, or technology nodes.
• Experience with FPGA prototyping, emulation, silicon bring-up, post-silicon debug, or performance optimization.
• Proficiency in scripting and workflow automation with Python, Tcl, Perl, or shell.
• Experience leading teams or mentoring technical staff in a matrixed engineering environment.
• Patents, publications, standards contributions, or technical thought leadership.

Culture & Benefits

• Regular, full-time employment in a hands-on individual-contributor and technical leadership role.
• Collaboration spans global engineering teams and architecture, design verification, physical design, firmware, software, emulation, FPGA prototyping, board, and post-silicon groups.
• Incentive opportunities reward individual and company performance.
• hirify.global uses artificial intelligence to screen, assess, or select applicants.