Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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$106к-154к/год
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У роли четкие профильные задачи и понятные требования, а Company hidden работает в области FPGA; при этом работа только из офиса и требования по экспортным разрешениям ограничивают доступность вакансии.
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Product Development Engineer (FPGA): Developing, validating, and productizing manufacturing test content for FPGAs with an accent on DFT strategies, MBIST flows, test coverage, and yield enhancement. Focus on simulating and debugging test patterns, analyzing silicon failures and customer returns, and reducing test time and product costs.
Location: San Jose, California, United States; Shift 1.
Salary: $106,200–$153,675 USD annually for the Bay Area, California.
Company
hirify.global develops programmable logic technology and FPGA products.
What you will do
Architect, develop, validate, and productize manufacturing test content for FPGAs to detect manufacturing defects.
Develop DFT strategies including scan insertion, BIST, test compression, and testability features with RTL design and verification teams.
Define test plans, patterns, and fault models, and develop MBIST manufacturing test flows and scripts.
Simulate and validate pre-silicon test patterns before tape-out; analyze test results, debug silicon failures, and determine root causes.
Collaborate with manufacturing and test teams to optimize test time, cost, quality, coverage, and yield.
Analyze customer returns and fallout data to close test holes and reduce test time.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering or a related field, with 3+ years of industry experience in IC design and IC test.
Experience with DFT methodologies including scan chains, Memory BIST, ATPG, boundary scan, test compression, IJTAG, and JTAG networks.
Experience with test development tools such as Tessent IJTAG, Tessent MemoryBIST, FastScan, and Tessent Shell.
Experience with RTL design, synthesis, and verification flows.
Experience with fault grading, test time analysis, test coverage analysis, and test yield enhancement.
Scripting skills in Python, Perl, TCL, or similar languages.
Knowledge of semiconductor manufacturing test processes and digital and analog circuit fundamentals.
Applicants must be eligible for any required U.S. export authorizations.
Nice to have
Master’s degree in Electrical Engineering or an equivalent or related Engineering degree.
Experience with Tessent MBIST flows for pattern development and knowledge of memory repair schemes and memory algorithms.
Post-silicon experience with pattern conversion, ATE pattern bring-up, and silicon characterization.
Culture & Benefits
Regular full-time position in the Manufacturing Content Development Engineering Group.
Incentive opportunities based on individual and company performance.
Work is associated with Shift 1 in the United States of America.
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