DFT Engineer (AI/ML)

Location: Hybrid, based in Santa Clara, CA; Austin, TX; or Fort Collins, CO, United States

Compensation: $100,000–$500,000, including base and variable compensation targets. Actual offers depend on experience, skills, education, background, and location.

Company

Tenstorrent develops high-performance AI platforms combining software models, compilers, platforms, networking, semiconductors, and RISC-V CPUs.

What you will do

• Implement and integrate scan, JTAG, compression, ASST, and MBIST features into RTL across multiple IPs from early design through tapeout.
• Own ATPG, test coverage analysis, and gate-level simulation using tools such as Synopsys VCS and Verdi.
• Plan, implement, and verify MBIST while collaborating with Test Engineering on test planning, pattern delivery, and debug.
• Develop and refine DFx flows and methodologies that integrate with front-end and physical design flows.
• Balance fault coverage, test cost, design intrusiveness, silicon bring-up, and yield learning.
• Collaborate with design, physical design, verification, test, and manufacturing teams on advanced ASICs.

Requirements

• BS, MS, or PhD in EE, ECE, CE, or CS.
• 5+ years of industry experience in advanced DFx/DFT for complex ASIC/SoC designs.
• Fluency in Verilog RTL for DFT logic, including lock-up latches, clock gates, and scan anchors.
• Comfort with SystemVerilog and UVM.
• Hands-on experience with ATPG and DFx insertion tools.
• Experience with stuck-at, transition, path-delay, IDDQ, and cell-aware fault models.
• Experience with low-power design flows.
• Strong debugging and problem-solving skills across design hierarchies, with effective collaboration across design, physical design, verification, and test teams.
• The applicant must be eligible to access U.S. export-controlled technology; employment may depend on citizenship, permanent residency, or prior license approval under U.S. export laws.

Culture & Benefits

• Collaborative environment with experienced engineers across ASIC design domains.
• Work on high-performance AI/ML chips with aggressive performance and power targets.
• Competitive compensation package and benefits.
• Equal opportunity employment.
• Offers are aligned with the experience level assessed during the interview process and may differ from the level in the posting.