RTL Design Engineer (AI)

Location: Palo Alto, CA, United States

Salary: $250,000–$400,000 per year

Company

Early-stage, venture-backed AI semiconductor startup developing a specialized accelerator and supporting software stack for efficient, high-performance LLM inference.

What you will do

• Translate architectural specifications into block-level microarchitecture and synthesizable RTL.
• Design and optimize datapaths, control logic, and inter-block interfaces.
• Make throughput, latency, power, area, and timing trade-offs and drive RTL improvements.
• Own RTL development, debugging, integration, verification closure, and tapeout readiness for assigned ASIC/SoC blocks.
• Collaborate with verification, microarchitecture, and physical design teams to resolve functional, timing, synthesis, and implementation issues.
• Document design decisions, implementation risks, and technical trade-offs.

Requirements

• Extensive digital hardware design experience with significant hands-on ownership of ASIC or SoC RTL development.
• Strong proficiency in Verilog and/or SystemVerilog.
• Proven ability to develop complex RTL from architectural specifications through implementation.
• Deep understanding of digital microarchitecture, including datapaths, state machines, control logic, concurrency, and cycle-level behavior.
• Strong knowledge of power, performance, and area optimization and the impact of RTL choices on physical implementation.
• Experience debugging complex RTL issues and resolving functional or timing-related challenges.
• Demonstrated collaboration with verification, microarchitecture, and physical design teams.
• Staff-to-Principal-level technical judgment with a willingness to remain hands-on in RTL design and debugging.

Nice to have

• Experience designing AI accelerators, inference ASICs, GPUs, or other high-performance compute silicon.
• Familiarity with LLM inference workloads and specialized compute architectures.
• Experience with synthesis, static timing analysis, and physical design feedback.
• Previous involvement in successful ASIC/SoC tapeouts.
• Background in first-generation silicon or early-stage hardware development.
• Experience collaborating across architecture, design verification, and physical implementation.

Culture & Benefits

• Significant ownership of RTL and microarchitecture for first-generation silicon.
• Direct collaboration with a highly technical founding engineering team.
• Hands-on environment with broad technical exposure and minimal organizational layers.
• Opportunity to influence architecture, design methodologies, and implementation strategies.

Hiring process

• Typically two to three conversations, including technical discussions about previous projects, RTL design experience, and engineering problem-solving.
• Further details about the team, architecture, and technology roadmap are shared under NDA as the process progresses.