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6 дней назад

Principal Design Engineer (ASIC)

185 000 - 240 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Principal Design Engineer (ASIC/AI Infrastructure): Developing front-end circuit designs and high-performance network controllers with an accent on micro-architecture, RTL, synthesis, IP integration, and block-level verification. Focus on PCIe, UALink, Esun, and Ethernet protocols, full-chip ownership through GDS and production, silicon bring-up, DFT, and small-geometry CMOS design.

Location: San Jose, California, United States. Authorized to work in the US and able to start immediately.

Base salary: $185,000–$240,000 USD annually, determined by location, experience, and compensation for similar positions.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and the COSMOS software suite.

What you will do

  • Develop micro-architecture and front-end circuit designs for high-performance network controllers.
  • Own RTL development, synthesis, IP integration, simulations, timing closure, GLS, and block-level verification.
  • Drive full-chip or block-level designs from architecture through GDS and production.
  • Work with PCIe, UALink, Esun, Ethernet, and other high-speed communication protocols.
  • Support silicon bring-up, debugging, DFT implementation, and scan test insertion.
  • Prioritize multiple tasks, prepare for customer meetings, and work with minimal guidance.

Requirements

  • Bachelor’s degree in Electrical Engineering required; Master’s degree preferred.
  • More than 8 years of experience supporting or developing complex SoC or silicon products for switch ASIC, networking, server, or storage applications.
  • Thorough hands-on knowledge of high-speed protocols, including PCIe, UALink, Esun, and Ethernet.
  • Proven front-end design expertise covering architecture, RTL, simulation, synthesis, timing closure, GLS, and DFT.
  • Experience owning full-chip or block-level designs from architecture to GDS and production.
  • Experience with Synopsys and/or Cadence digital design tools and flows.
  • Knowledge of DFT, stuck-at testing, and transition scan test insertion.
  • Familiarity with UVM-based design verification, silicon bring-up, and debugging.
  • Experience designing with small-geometry CMOS at 28 nm or smaller.
  • US work authorization required.
  • Professional attitude, ability to manage changing priorities, customer focus, entrepreneurial mindset, and can-do attitude.

Nice to have

  • Firmware development in C.
  • Scripting with Python or equivalent programming languages.
  • Experience developing or supporting PCIe or Ethernet switch products.
  • Master’s degree in Electrical Engineering.

Culture & Benefits

  • Work on rack-scale AI infrastructure and custom connectivity solutions for hyperscalers and ecosystem partners.
  • Collaborative environment built around diverse ideas, backgrounds, and experiences.
  • Applications are encouraged from people with relevant experience across diverse backgrounds, including veterans, parents, people with disabilities, LGBTQ+ and non-binary people, and people of color.

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