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4 дня назад

Design Engineering Architect – Systems and Interfaces (SoC/RTL)

185 500 - 344 500$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Design Engineering Architect – Systems and Interfaces (SoC/RTL): Enabling the integration and deployment of Cadence interface IP in complex customer SoCs with an accent on RTL design, verification, system architecture, and high-speed interface protocols. Focus on leading customer engagements, resolving complex integration issues, developing reference designs and technical content, and driving product readiness across cross-functional engineering teams.

Location: San Jose, California, or Austin, Texas, United States; travel up to 10% internationally.

Annual salary: $185,500–$344,500, plus potential bonus, equity, and benefits.

Company

hirify.global develops and licenses IP for SoC and ASIC designs, including DSPs, CPUs, interface IP, DDR controllers, hardware accelerators, and subsystems used in machine learning, edge AI, radar, audio, speech, and vision applications.

What you will do

  • Serve as the technical authority for interface controllers and system-level IP integration in customer engagements.
  • Lead critical customer issue resolution and escalations across pre-sales and post-sales engagements.
  • Develop reference designs, technical collateral, application notes, and customer and field application engineer training.
  • Provide advanced guidance on IP integration, configuration, and system-level deployment.
  • Lead product evaluations and release-readiness reviews, identifying integration risks, usability gaps, and advanced customer use cases.
  • Propose product and documentation enhancements based on customer needs and use cases.

Requirements

  • Expertise in RTL design, verification, and debug of high-speed interface protocols such as PCIe, UCIe, and Ethernet.
  • Experience integrating IP into complex SoCs, including system architecture, interfaces, and on-chip interconnects.
  • Experience with AMBA protocols, including ACE, CHI, AXI, and APB.
  • Proficiency in writing and debugging RTL using Verilog and SystemVerilog.
  • Experience with end-to-end SoC implementation flows, including RTL synthesis, design constraints, DFT, CDC, and static timing analysis.
  • Ability to analyze complex hardware and system problems, identify root causes, and drive cross-functional teams to resolution.
  • Strong written and verbal communication skills.
  • BS in EE/CS with 12+ years or MS in EE/CS with 8+ years of relevant experience.

Culture & Benefits

  • Full-time employment with paid vacation and paid holidays.
  • 401(k) plan with employer match and employee stock purchase plan.
  • Medical, dental, and vision plan options.
  • Potential incentive compensation through bonus, equity, and benefits.

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