Principal VLSI/ASIC Design Engineer (ASIC)

Location: Hybrid in Sunnyvale, California, United States; work from an HPE office an average of 2 days per week

Annual base salary: USD 181,000–367,000 in California; variable incentives may also be offered.

Company

hirify.global is an edge-to-cloud technology company developing solutions that connect, protect, analyze, and process data and applications.

What you will do

• Lead early-stage ASIC architecture and design exploration for networking, compute, and complex SoC applications.
• Define architectures, microarchitectures, design methodologies, and implementation plans aligned with product requirements and technology roadmaps.
• Develop complex RTL and drive designs through synthesis, physical implementation support, timing closure, and production readiness.
• Analyze performance, power, area, scalability, reliability, cost, risk, and schedule tradeoffs through modeling, simulation, prototyping, and evaluation.
• Conduct design reviews, establish ASIC methodologies and standards, and integrate new technologies, IP, tools, and implementation improvements.
• Provide technical leadership across architecture, hardware, firmware, verification, physical design, systems, software, manufacturing, suppliers, and external partners; mentor engineers.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; equivalent experience may be considered.
• Typically 9+ years of experience in ASIC, VLSI, SoC, or related hardware design, including complex RTL design for networking, compute, communications, storage, or other advanced SoC applications.
• Experience leading architecture and design exploration through RTL implementation and product integration.
• Advanced knowledge of ASIC and VLSI design principles, digital logic, RTL design, and SoC development.
• Proven experience with complex RTL using Verilog, SystemVerilog, or comparable hardware description languages.
• Knowledge of ASIC flows covering architecture, microarchitecture, RTL coding, synthesis, timing analysis, physical design interaction, and design signoff.
• Experience with design modeling, simulation, performance analysis, empirical evaluation, and improving design methodologies, tools, automation, and engineering practices.
• Strong analytical, problem-solving, technical decision-making, communication, collaboration, and influencing skills across business units, senior leadership, external partners, and industry organizations.
• Ability to mentor engineers and provide technical direction without direct management responsibility.

Nice to have

• Experience with networking ASICs, data-processing units, switching, routing, acceleration, storage, or high-performance computing architectures.
• Experience with high-speed interfaces, packet-processing pipelines, memory subsystems, interconnects, or performance-critical datapaths.
• Familiarity with formal verification, constrained-random verification, coverage methodologies, or verification planning.
• Experience with low-power design, clock-domain crossing, reset-domain crossing, DFT, and design-for-reuse methodologies.
• Knowledge of industry standards and leading-edge ASIC implementation technologies.
• Experience with outsourced development partners, IP vendors, foundries, or semiconductor suppliers.
• Design verification experience is desirable but not required.

Culture & Benefits

• Hybrid work arrangement with an average of two office days per week.
• Health, financial, and emotional wellbeing benefits for employees and their loved ones.
• Personal and professional development programs supporting career growth and knowledge expertise.
• Inclusive workplace focused on flexibility, varied backgrounds, collaboration, and engineering excellence.

Hiring process

• Accessibility accommodations are available during any stage of the application or interview process through HPE’s candidate support form.