Sr. Principal VLSI/ASIC Design Engineer (ASIC)

Location: Hybrid in Sunnyvale, California, United States; work from an HPE office an average of 2 days per week.

Salary: USD 181,000–367,000 annual base salary in California; variable incentives may also be offered.

Company

hirify.global is a global edge-to-cloud company developing infrastructure and technologies that connect, protect, analyze, and process data and applications.

What you will do

• Lead early-stage ASIC architecture and design exploration for complex networking, compute, and SoC applications.
• Define architectures, microarchitectures, design methodologies, and implementation plans aligned with product requirements and technology roadmaps.
• Develop complex RTL blocks and drive implementation through synthesis, physical design support, timing closure, and production readiness.
• Evaluate performance, power, area, scalability, reliability, cost, risk, and schedule through modeling, simulation, prototyping, and experimental analysis.
• Conduct design reviews, establish organization-wide ASIC methodologies and standards, and integrate new technologies, IP, and implementation improvements.
• Provide technical leadership across architecture, hardware, firmware, verification, physical design, systems, software, manufacturing, suppliers, and external partners; mentor engineers and influence strategic decisions.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; equivalent experience may be considered.
• Typically 11+ years of experience in ASIC, VLSI, SoC, or related hardware design, including experience designing complex RTL blocks for networking, compute, communications, storage, or other advanced SoC applications.
• Experience leading architecture and design exploration through RTL implementation and product integration.
• Advanced knowledge of ASIC and VLSI design principles, digital logic, RTL design, and SoC development.
• Proven experience developing complex RTL using Verilog, SystemVerilog, or comparable hardware description languages.
• Understanding of ASIC flows covering architecture, microarchitecture, RTL coding, synthesis, timing analysis, physical design interaction, and design signoff.
• Experience with design modeling, simulation, performance analysis, empirical evaluation, design methodologies, tools, automation, and engineering practices.
• Strong analytical, problem-solving, technical decision-making, written and verbal communication, collaboration, and innovation skills.
• Ability to communicate architectural proposals, tradeoffs, risks, and results; influence decisions across business units, leadership, partners, and industry organizations; and mentor engineers without direct management responsibility.

Nice to have

• Design verification experience, including formal verification, constrained-random verification, coverage methodologies, or verification planning.
• Experience with networking ASICs, data-processing units, switching, routing, acceleration, storage, high-performance computing, high-speed interfaces, packet-processing pipelines, memory subsystems, interconnects, or performance-critical datapaths.
• Experience with low-power design, clock-domain crossing, reset-domain crossing, DFT, and design-for-reuse methodologies.
• Knowledge of industry standards and leading-edge ASIC implementation technologies.
• Experience working with outsourced development partners, IP vendors, foundries, or semiconductor suppliers.

Culture & Benefits

• Hybrid work arrangement with an average of 2 office days per week in Sunnyvale.
• Health, financial, and emotional wellbeing benefits for employees and their loved ones.
• Personal and professional development programs supporting career growth and knowledge expertise.
• Inclusive workplace committed to accessibility, equal opportunity, and respect for varied backgrounds.
• Variable incentives may be offered in addition to the listed base salary.