Senior Lead Engineer - Design Verification (FPGA)

Location: San Jose, California, United States. Applicants must be eligible for any required U.S. export authorizations.

Salary: $231,500–$330,000 USD annually for the Bay Area California region; incentive opportunities are also available.

Company

hirify.global develops FPGA, programmable SoC, and platform solutions.

What you will do

• Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems across block, subsystem, and full-chip levels.
• Translate architecture and product requirements into functional, performance, resilience, and coverage objectives.
• Architect reusable SystemVerilog/UVM environments, verification IP, scoreboards, reference models, constrained-random stimulus, checkers, and coverage models.
• Advance verification methodology, coding standards, testbench guidelines, regression practices, automation, and reporting infrastructure.
• Drive coverage closure, risk assessment, root-cause analysis, and resolution of simulation, integration, and system-level failures.
• Collaborate with architecture, RTL, CAD, emulation, firmware/software, board, physical design, and post-silicon teams while mentoring verification engineers.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, plus 15+ years of relevant design verification experience in FPGA, ASIC, SoC, or semiconductor products; an advanced degree is preferred.
• Technical leadership delivering verification from architecture through RTL verification, integration, full-chip verification, and hardware or silicon validation.
• Deep expertise in SystemVerilog and UVM, including constrained-random verification, assertions, self-checking environments, testbench architecture, functional coverage, and coverage-driven closure.
• Experience creating reusable verification IP, UVM frameworks, testbench components, or methodology adopted across multiple blocks, teams, or programs.
• Experience verifying high-performance digital architectures such as networking or packet-processing datapaths, memory subsystems, on-chip interconnect, PCIe/CXL, Ethernet, high-speed I/O, or programmable acceleration.
• Strong understanding of RTL design, microarchitecture, simulation, debug, formal or static verification concepts, and hardware development flows.
• Experience with regression management, simulation build and execution flows, test automation, and data-driven verification reporting.
• Ability to collaborate and influence across architecture, RTL design, CAD, emulation, firmware/software, system validation, and product engineering organizations.
• Strong written and verbal communication skills for communicating verification strategy, risk, closure status, and technical recommendations.

Nice to have

• Experience with FPGA architectures, programmable-logic devices, configurable interconnect, SmartNICs, IPUs, SoCs, or data-center acceleration platforms.
• Experience with C/C++, SystemC, Python, Tcl, Perl, or shell scripting for reference models, automation, testbench infrastructure, or verification productivity.
• Experience with formal verification, low-power verification, CDC/RDC analysis, performance verification, or hardware-accelerated verification environments.
• Experience with full-chip verification, processor-based test development, firmware/software co-verification, or post-silicon debug.
• Experience leading verification methodology or mentoring engineers in a matrixed engineering environment.
• Patents, publications, standards contributions, or sustained methodology leadership.

Culture & Benefits

• Regular full-time employment on Shift 1 in the United States.
• Incentive opportunities based on individual and company performance.
• Work involves collaboration across global, cross-functional engineering teams.
• AI is used to screen, assess, or select applicants.