SoC Design Engineer (NAND Flash SSD Controllers)

Location: San Jose, CA, United States

Salary: $167,360–$267,800 per year

Company

hirify.global is a global memory technology company developing NAND technologies and optimized data storage solutions, with U.S. headquarters and international operations.

What you will do

• Architect, design, and implement complex synthesizable RTL modules for NAND Flash memory-based SSD controllers using Verilog/SystemVerilog.
• Translate system requirements into microarchitecture and optimize controller pipelines, state machines, arbitration logic, queues, FIFOs, DMA engines, and memory interfaces.
• Develop NAND command sequencing, interface control, data transfer, status handling, error recovery, timing management, and parallel-operation support.
• Optimize designs for throughput, latency, timing, power, and silicon area using synthesis and static timing analysis results.
• Drive RTL through lint, CDC/RDC, subsystem integration, ASIC implementation handoff, emulation, silicon bring-up, and post-silicon debug.
• Integrate reliability logic including ECC/LDPC, error detection, recovery sequencing, fault handling, and data-protection mechanisms while collaborating across engineering teams.

Requirements

• Master’s or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Typically 3+ years of relevant experience in RTL design and ASIC development.
• Strong proficiency in Verilog/SystemVerilog and experience designing complex, synthesizable RTL.
• Deep understanding of digital logic, sequential design, finite-state machines, pipelining, timing closure, and computer architecture.
• Experience with ASIC design flows, including RTL simulation, lint, synthesis, static timing analysis, and design integration.
• Experience analyzing timing reports and optimizing RTL for performance, power, and area requirements.
• Strong understanding of clocking, reset architecture, CDC, and robust hardware design practices.
• Proficiency in scripting or programming with Python, Tcl, Perl, or C/C++ for design automation and result analysis.
• Ability to debug complex hardware issues, perform root-cause analysis, and collaborate across engineering teams.

Nice to have

• Experience designing NAND Flash controllers, SSD controllers, or other high-performance storage ASICs.
• Understanding of SSD architecture, FTL interactions, NAND parallelism, storage data paths, ONFI, and Toggle-mode interfaces.
• Knowledge of NAND reliability, error management, ECC/LDPC, bad-block handling, and read-retry mechanisms.
• Experience with high-throughput data paths, DMA engines, queue management, arbitration, buffering, and memory interfaces.
• Familiarity with EDA tools for simulation, synthesis, lint, CDC/RDC, and static timing analysis.
• Experience with low-power design, clock gating, power management, PPA optimization, formal verification, emulation, FPGA prototyping, or post-silicon debug.
• Understanding of AXI, AHB, PCIe, or NVMe-related controller interfaces.
• Experience with design automation, RTL quality analysis, or AI-assisted hardware design and verification workflows.
• Technical ownership and delivery of complex ASIC designs from specification through silicon validation.

Culture & Benefits

• Collaborative, inclusive, customer-inspired, innovative, and results-driven working environment.
• Medical, dental, vision, supplemental life, AD&D, and short- and long-term disability insurance.
• Healthcare and dependent-care flexible spending accounts.
• Company match on eligible 401(k) contributions.
• Eligibility for restricted stock units, restricted cash units, and cash bonus programs.