Senior Lead Design Engineer - RTL Design (FPGA)

Location: San Jose, California, United States; Shift 1; applicants must be eligible for required U.S. export authorizations.

Salary: $231,500–$330,000 USD annually for the Bay Area California location, plus incentive opportunities.

Company

hirify.global develops FPGA, programmable SoC, and programmable technology solutions.

What you will do

• Lead RTL architecture, microarchitecture, implementation, and subsystem integration for FPGA, programmable SoC, and infrastructure-class solutions.
• Design reusable, synthesizable, scalable, and testable RTL for high-throughput datapaths, memory access, interconnect, packet and data processing, and programmable acceleration.
• Define specifications, interface contracts, clocking and reset strategies, performance targets, and implementation plans across architecture, verification, physical design, firmware, software, and product teams.
• Drive tradeoffs involving throughput, latency, bandwidth, buffering, power, area, timing, reliability, scalability, cost, and schedule.
• Advance RTL methodologies covering coding standards, lint, CDC/RDC, synthesis, formal checks, automation, and design reviews.
• Lead verification strategy, complex issue debug, technical risk mitigation, mentorship, architecture reviews, and collaboration through implementation, validation, and product delivery.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline, plus 15+ years of relevant experience in FPGA, ASIC, SoC, or semiconductor product development; an advanced degree is preferred.
• Technical leadership delivering complex digital designs from architecture and microarchitecture through RTL, verification, integration, implementation, and post-silicon or hardware validation.
• Deep hands-on expertise in Verilog and/or SystemVerilog RTL development, synthesis, lint, CDC/RDC, formal or equivalence checking, timing constraints, and implementation-aware design.
• Experience designing high-performance digital subsystems such as network or data-processing pipelines, memory controllers or subsystems, on-chip interconnect, traffic-management logic, PCIe/CXL, Ethernet, high-speed interfaces, or programmable acceleration engines.
• Strong understanding of bandwidth, latency, congestion, buffering, throughput, power, area, timing, and reliability tradeoffs at the architectural and RTL levels.
• Experience leading execution across multiple functional blocks or complex subsystem integration, including technical planning, risk management, schedule alignment, and prioritization.
• Ability to collaborate and influence across architecture, design verification, physical design, DFT, CAD, firmware/software, system validation, and product engineering organizations.
• Strong written and verbal communication skills for communicating design intent, technical risks, and recommended solutions.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Experience with FPGA architectures, programmable-logic devices, configurable interconnect, SmartNICs, IPUs, SoCs, or data-center acceleration platforms.
• Experience building, maintaining, or deploying reusable RTL IP across multiple products, technology nodes, or programs.
• Experience with high-bandwidth memory architectures, packet buffering, lookup or classification engines, flow control, or high-speed connectivity subsystems.
• Experience with FPGA prototyping, emulation, silicon bring-up, post-silicon debug, or performance optimization.
• Proficiency in Python, Tcl, Perl, or shell scripting and workflow automation.
• Technical leadership demonstrated through patents, publications, standards contributions, or sustained methodology innovation.

Culture & Benefits

• Regular full-time employment in a hands-on Principal Engineer-level individual-contributor role.
• Collaboration spans global engineering teams and architecture, verification, physical design, CAD, DFT, emulation, firmware, software, board, and post-silicon organizations.
• Incentive opportunities reward individual and company performance.