Design Engineer - STA (ASIC)

Location: Fort Collins, Colorado, USA; onsite at 4380 Ziegler Road

Annual base salary: USD 129,400–207,000, plus discretionary annual bonus and equity awards.

Company

hirify.global's ASIC Products Division develops custom CMOS ASICs for AI, cellular, networking, computing, and storage products.

What you will do

• Develop, validate, and maintain timing constraints for complex SoCs across multiple modes and process corners.
• Perform pre- and post-route static timing analysis, QoR evaluation, timing closure, and signoff using Synopsys PrimeTime or Cadence Tempus.
• Define timing signoff methodologies, including derates, uncertainties, PVT corners, and advanced STA techniques.
• Generate and validate timing ECOs and debug timing violations, signal integrity issues, crosstalk, noise, and clock network challenges.
• Automate timing flows and analysis with Tcl and scripting languages while supporting power and performance optimization.
• Collaborate with physical design, synthesis, clock, external customer, and global design teams; provide technical leadership and improve methodologies.

Requirements

• BS in Electrical or Computer Engineering with 12+ years of relevant experience, or MS in Electrical or Computer Engineering with 10+ years of relevant experience.
• Deep understanding of VLSI design principles and ASIC physical design fundamentals.
• Experience creating, debugging, and validating timing constraints, including setup/hold analysis, MMMC timing, ECO convergence, and timing signoff.
• Working knowledge of PLLs, clock network design, flip-flops, latches, and memories.
• Strong understanding of RC networks, signal integrity, crosstalk delay, and noise analysis.
• Strong Tcl scripting experience and proficiency with Linux/UNIX environments.
• Excellent communication, analytical, problem-solving, organizational, and data-presentation abilities, with independent engineering judgment.

Nice to have

• Proficiency in Python, Perl, or Ruby.
• Hands-on experience with Synopsys and/or Cadence STA tools.
• Exposure to POCV, SOCV, LVF, PBA, SPICE correlation, CCS/ECSM/NLDM timing libraries, and multi-input switching effects.
• Experience mentoring others and driving methodology improvements.

Culture & Benefits

• Work with a cross-functional and global engineering organization on high-performance SoCs operating above 1 GHz and using 3 nm and smaller process nodes.
• Medical, dental, and vision plans; 401(k) participation with company matching; and Employee Stock Purchase Program.
• Employee Assistance Program, company-paid holidays, paid sick leave, vacation time, and applicable paid family and other leave.
• Annual bonus eligibility, competitive new-hire equity grants, and annual equity awards, subject to applicable plans and agreements.
• hirify.global is an equal opportunity employer and considers qualified applicants without regard to protected characteristics or legally protected records.

Hiring process

• First-time applicants must create a candidate login account before applying; existing candidates must sign in before applying.
• Applicants located outside the USA should provide a home address for future correspondence.