Назад
Company hidden
9 дней назад

Principal Physical Design Engineer (ASIC)

143 800 - 230 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Principal Physical Design Engineer (ASIC): Leading block-level and top-level physical implementation for high-performance networking, AI/ML accelerator, and custom cloud ASICs with an accent on advanced-node floorplanning, place and route, clock-tree synthesis, timing closure, and signoff. Focus on executing 3nm/2nm tapeouts, optimizing multi-corner multi-mode timing and power, and automating EDA flows for ultra-large-scale silicon.

Location: San Jose, California, United States

Annual base salary: USD 143,800–230,000

Company

hirify.global’s ASIC Products Division develops custom high-performance silicon solutions for hyperscale cloud providers, AI companies, and networking infrastructure leaders.

What you will do

  • Lead block-level and top-level physical implementation from floorplanning through GDSII stream-out using Cadence Innovus.
  • Execute placement, clock-tree synthesis, routing, and timing and power optimization on 5nm, 3nm, and 2nm technology nodes.
  • Perform MCMM static timing analysis, signal-integrity optimization, and power-grid signoff, including IR-drop and electromigration analysis.
  • Drive implementation for networking, AI/ML accelerator, and custom cloud ASICs, collaborating across architecture, design, and manufacturing functions.
  • Develop and improve automated physical-design methodologies and EDA flows.

Requirements

  • B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • 12+ years of hands-on physical design experience with successful tapeouts of complex, high-frequency, ultra-large-scale networking or AI ASICs.
  • Direct tapeout experience in TSMC N7, N5, N3, or equivalent advanced foundry processes.
  • High proficiency with Cadence Innovus for place and route; Synopsys PrimeTime or Cadence Tempus for timing and STA; StarRC or QRC and RedHawk for extraction and IR/EM; and Siemens Calibre for DRC/LVS.
  • Advanced TCL, Python, and Unix shell scripting for flow automation and database manipulation.
  • Strong technical leadership, problem-solving, and cross-functional communication skills.

Nice to have

  • Experience implementing high-speed clock networks, including H-tree, mesh, and low-power CTS.
  • Experience with power-aware implementation flows, UPF/CPF, multi-voltage domains, and clock or power gating.

Culture & Benefits

  • Full-time employment with medical, dental, and vision plans.
  • 401(k) participation with company matching, ESPP, and EAP.
  • Company-paid holidays, paid sick leave, vacation time, and applicable paid family and other leave.
  • Eligibility for a discretionary annual bonus, new-hire equity grant, and annual equity awards, subject to plan documents and award agreements.
  • Equal opportunity employment is provided in accordance with applicable federal, state, and local law.

Hiring process

  • First-time applicants must create a candidate login account before applying; existing candidates must sign in before applying.
  • Applicants located outside the United States should provide a home address for future correspondence.

Будьте осторожны

Если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого. Это мошенники. Обязательно жмите «Пожаловаться» или пишите в поддержку. Подробнее в гайде →