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4 дня назад

IC Design Engineer (STA/Synthesis)

143 800 - 230 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior/lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Lead IC Design Engineer (STA/Synthesis) (ASIC/SoC): Developing timing constraints, synthesis flows, static audits, and timing signoff for mission-critical IP and ASIC blocks in advanced technology nodes with an accent on static timing analysis, clock-tree optimization, and timing closure. Focus on automating analysis with Tcl or Perl, resolving complex timing issues through ECOs, and validating signoff quality across process corners, derates, and uncertainties.

Location: San Jose, California, United States; onsite role

Annual base salary: USD 143,800–230,000

Company

hirify.global develops semiconductor technologies and mission-critical IP and ASIC solutions.

What you will do

  • Develop and validate timing constraints for complex hierarchical SoC designs.
  • Perform static timing analysis using PrimeTime, TCM, Tempus and related industry tools.
  • Run synthesis and static audits covering CDC, RDC, low power and equivalence for complex digital and mixed-signal blocks.
  • Define timing signoff methodologies, including process corners, derates, uncertainties, checklists and criteria.
  • Conduct pre-route timing and QoR analysis, generate timing ECOs and drive timing closure.
  • Automate timing analysis with Tcl or Perl and guide clock-tree synthesis and optimization for energy-efficient designs.

Requirements

  • Experience with high-complexity silicon in advanced technology nodes.
  • Experience developing timing constraints for hierarchical designs and knowledge of clock-tree planning and implementation for SoCs.
  • Experience creating timing ECOs and completing final timing signoff.
  • Proficiency with STA tools such as PrimeTime, TCM and Tempus, and scripting languages such as Tcl and Perl.
  • Proficiency with synthesis and audit tools including DC-T, Genus, Fishtail, VCLP and Formality.
  • Strong understanding of ASIC design flows, including RTL and place-and-route.
  • Strong problem-solving, attention to detail, communication and teamwork skills, with the ability to work independently in a fast-paced, cross-geographical environment.
  • At least a Bachelor’s degree and 12+ years of related experience, a Master’s degree and 10+ years, or a PhD and 7+ years; post-graduate coursework is highly desirable at this level.

Nice to have

  • Direct or indirect experience with RTL/design.

Culture & Benefits

  • Full-time employment with medical, dental and vision plans.
  • 401(k) participation with company matching, ESPP and EAP.
  • Company-paid holidays, paid sick leave, vacation and applicable paid family leave and other leaves of absence.
  • Eligibility for a discretionary annual bonus, competitive new-hire equity grants and annual equity awards, subject to plan documents and award agreements.
  • Equal-opportunity employment practices apply.

Hiring process

  • First-time applicants must create a candidate login account before applying; existing candidates must sign in before applying.
  • Applicants located outside the United States should provide a home address for future correspondence.

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