Physical Design Engineer (ASIC)

Location: San Jose, California, United States; onsite role. Legal authorization to work in the U.S. is required.

Annual base salary: USD 82,500–132,000, plus discretionary bonus and equity awards.

Company

hirify.global's ASIC Products Division develops custom high-performance silicon solutions for hyperscale cloud providers, AI companies, and networking infrastructure leaders.

What you will do

• Execute block-level floorplanning and placement-and-route flows using industry-standard EDA tools.
• Perform static timing analysis, debug timing paths, and implement ECOs for timing closure.
• Run physical verification checks, including DRC, LVS, ERC, and antenna checks, and resolve signoff violations.
• Analyze IR drop and electromigration to maintain power-grid integrity.
• Develop and maintain automation scripts in TCL, Python, Ruby, or Bash to improve flow efficiency.
• Support implementation of next-generation networking, AI/ML accelerator, and custom cloud ASICs across advanced N5/N3/N2/A14 nodes.

Requirements

• Bachelor's degree in Electrical Engineering or Computer Engineering plus 2 years of experience, or a Master's degree in Electrical Engineering or Computer Engineering with graduation within the past 12 months.
• Solid understanding of digital CMOS logic design, standard-cell libraries, and semiconductor fundamentals.
• Familiarity with static timing analysis concepts, clocking, and setup/hold timing.
• Hands-on coursework, laboratory experience, or academic projects using EDA design tools such as Cadence Innovus/Tempus, Synopsys IC Compiler II/PrimeTime, or Siemens tools.
• Proficiency in TCL, Python, Ruby, or Bash scripting.
• Legal authorization to work in the United States is required.

Nice to have

• Internship or research experience in ASIC physical design, synthesis, or physical verification.
• Basic understanding of Design for Testability, low-power intent using UPF/CPF, and FinFET technologies.
• Excellent problem-solving, debugging, and analytical skills.

Culture & Benefits

• Work with experienced engineers on complex ASICs using advanced physical-design methodologies and 2.5D/3D chiplet integration.
• Medical, dental, and vision plans, 401(k) participation with company matching, and an Employee Stock Purchase Program.
• Employee Assistance Program, company-paid holidays, paid sick leave, vacation time, and applicable paid family and other leave.
• Discretionary annual bonus, competitive new-hire equity grant, and potential annual equity awards subject to plan documents and award agreements.

Hiring process

• First-time applicants must create a candidate login account before applying; existing candidates must sign in before applying.