Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
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$144к-230к/год
$160к$190кмедиана$190к
По похожим ролям (50) ~ $190к/год
На СНГ рынке: $2.5к/мес ($1.9к - $3.1к)
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Крутая вакансия
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В Company hidden это четко очерченная ведущая роль в проектах передовых ASIC с большой ответственностью за timing sign-off и AI-методологии; порог в 12 лет опыта делает вакансию узкоспециализированной.
Передовые чипы
Четкая зона ответственности
?Высокий порог опыта
?Работа в офисе
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Principal Physical Design Engineer, STA (ASIC/AI): Delivering full-chip static timing sign-off and timing closure for advanced custom ASICs across PVT corners, with an accent on 3nm/2nm nodes, MMMC analysis, and AI-driven EDA automation. Focus on authoring SDC constraints, reducing STA runtime through machine learning, triaging timing violations, and driving ECOs across complex clock networks and multi-die designs.
Location: San Jose, California, United States; onsite role.
Annual base salary: USD 143,800–230,000, plus discretionary annual bonus and equity awards.
Company
hirify.global's ASIC Products Division develops custom high-performance silicon solutions for hyperscale cloud providers, AI platforms, and networking infrastructure.
What you will do
Own full-chip timing sign-off and final timing closure across PVT corners.
Author and maintain SDC constraints for functional and test modes.
Deploy AI/ML automation, data-mining workflows, and corner-reduction methods to reduce STA runtime and improve infrastructure efficiency while maintaining physical coverage.
Triage timing violations, identify root causes, and eliminate design marginalities across complex clock networks and multi-die boundaries.
Apply advanced OCV, SI, and IR-drop concepts and drive timing ECOs.
Collaborate with RTL, Physical Design, and DFT teams to optimize PPA.
Requirements
Bachelor's degree in Electrical Engineering or Computer Engineering.
12+ years of hands-on ASIC STA and timing closure experience.
Expert proficiency with sign-off tools including PrimeTime and Tempus.
Advanced experience with MMMC and OCV management.
Strong scripting skills in Tcl, Python, Perl, and Shell.
Proven use of AI plugins and data-mining scripts for runtime reduction and reporting.
Exceptional problem-solving and communication abilities.
Culture & Benefits
Work on advanced custom ASICs using 3nm/2nm technologies, 2.5D/3D chiplet integration, CoWoS, and HBM3/4.
Medical, dental, and vision plans; 401(k) participation with company matching; and an Employee Stock Purchase Program.
Employee Assistance Program, company-paid holidays, paid sick leave, vacation time, and applicable paid family and other leave.
First-time applicants must create a candidate login account before applying; existing candidates must sign in before applying.
Applicants located outside the USA should provide a home address for future correspondence.
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