Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Высокий порог входаПерспективная областьПонятные обязанности
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Staff Engineer, DFT (Semiconductor): Developing low-power DFT architectures and test infrastructure for ultra-low-power SoCs with an accent on scan insertion, boundary scan, MBIST, ATPG, and structural test coverage. Focus on hierarchical DFT implementation, pre/post-layout simulation, timing and constraint development, and bringing test vectors up on silicon.
Location: Austin, Texas, United States
Company
hirify.global develops ultra-low-power semiconductor solutions for AI edge applications, wearables, medical devices, IoT products, and other intelligent connected devices.
What you will do
Implement scan insertion, boundary scan, MBIST, and ATPG for ultra-low-power SoCs using standard EDA tools.
Develop low-power DFT architecture and infrastructure, including hierarchical structures for complex SoCs.
Generate structural test vectors and improve test coverage, test time, and test cost.
Perform pre- and post-layout scan and MBIST simulations.
Collaborate with designers on STA, physical, power, and logical issues related to DFT.
Work with test engineers to bring up test vectors on silicon and support production test.
Requirements
BS or MS in ECE or EE and at least 8 years of experience in DFT implementation.
Experience with scan structures, including Stuck-At, At-Speed, and Path-Delay testing, scan compression, boundary scan, and MBIST.
Experience creating and implementing hierarchical DFT architecture in complex SoCs.
Experience with low-power DFT and MBIST, including test-time and test-coverage analysis for scan and MBIST patterns.
Experience working with test engineering teams to bring up production test programs.
Extensive knowledge of timing concepts and constraint development.
Experience developing scan ATPG and MBIST test benches and running simulations in pre- and post-layout environments.
RTL experience is required.
Strong verbal and written English communication skills.
Self-driven approach, motivation, and attention to detail.
Nice to have
Scripting experience, such as Tcl.
Experience with GLS and gate-level simulation.
Culture & Benefits
Cross-functional collaboration across design, research, development, production, marketing, sales, and operations.
Work on complex semiconductor and energy-efficiency challenges for AI edge applications.
Values include innovation, collaboration, focus, learning, and achievement.
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