physical designasicsocformal verificationplace and routetiming analysisstapower optimizationphysical verification7nm
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
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$144к-230к/год
$140к$160кмедиана$190к
По похожим ролям (50) ~ $160к/год
На СНГ рынке: $2.5к/мес ($1.9к - $3.1к)
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Крутая вакансия
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Чётко описанная senior-вакансия в крупной полупроводниковой компании предполагает серьёзную ответственность за ASIC/SoC-дизайн, но требование 10-12+ лет опыта заметно сужает круг подходящих специалистов.
Требуют большой стаж
Понятные задачи
Крупный игрок отрасли
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Physical Design Engineer (ASIC/SoC) (Place and Route/Timing Closure): Implementing ASIC and SoC designs through floor-planning, placement, clock tree synthesis, routing, timing closure, physical verification, and power optimization with an accent on PPA metrics and right-first-time silicon. Focus on performing STA and equivalence checks, implementing timing and functional ECOs, and closing complex designs at block and full-chip level.
Location: San Jose, California, United States; additional locations in Allentown, Fort Collins, and Broomfield, United States.
Annual base salary: USD 143,800–230,000.
Company
hirify.global develops semiconductor and technology products.
What you will do
Execute ASIC and SoC design implementation across floor-planning, partitioning, placement, clock tree synthesis, routing, timing analysis, timing closure, and physical verification.
Drive tools and methodologies to achieve PPA targets and meet design milestones.
Perform equivalence checks, static timing analysis, timing closure, and power optimization.
Implement timing and functional engineering change orders.
Apply design methodology and milestone flows to achieve right-first-time silicon.
Requirements
Primary expertise in place and route and/or timing, including constraints and STA.
Proficiency in design implementation at both block and SoC level.
Hands-on experience with timing analysis and place-and-route tools for ASIC/SoC design.
Experience with floor-planning, partitioning, placement, clock tree synthesis, routing, physical verification, constraints development and validation, timing analysis, and closure.
Experience with formal verification, timing analysis, and ECO implementation.
BS in Electrical Engineering, Computer Engineering, or a related field with 12+ years of related experience, or MS in the same fields with 10+ years of related experience.
Ability to solve problems, work independently, learn and adapt to new tools and methodologies, and communicate effectively in a global, dynamic environment.
Nice to have
Experience with PrimeTime, ICC2, Innovus, Calibre, and LEC.
Full-chip tapeout experience using 7nm or smaller technologies.
Culture & Benefits
Full-time employment in a global and dynamic environment.
Eligible for a discretionary annual bonus, new-hire equity, and annual equity awards, subject to plan documents and award agreements.
Medical, dental, and vision plans; 401(k) with company matching; and an employee stock purchase program.
Employee assistance program, paid holidays, paid sick leave, vacation, and applicable family and other leave.
Applicants located outside the United States should provide a home address for future correspondence.
Hiring process
First-time applicants must create a candidate login account before applying; existing candidates must sign in before applying.
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