Senior Lead Engineer - Design and Architecture

Location: San Jose, California, United States

Salary: $231,500–$330,000 annually for the Bay Area California region; incentive opportunities are also offered.

Company

hirify.global develops programmable device portfolios and related high-performance silicon and platform subsystems for AI, cloud, networking, and edge applications.

What you will do

• Define system, subsystem, and microarchitecture for complex SoC, ASIC, and FPGA-adjacent platforms.
• Lead architecture exploration and tradeoffs across performance, power, area, bandwidth, latency, reliability, scalability, cost, and schedule.
• Develop architectural specifications, performance models, and implementation plans across hardware, firmware, software, validation, and product teams.
• Own architecture and design decisions from concept and RTL through integration, verification, emulation, bring-up, performance debugging, and production readiness.
• Provide technical leadership for on-chip networks, routing, arbitration, flow control, memory coherency, memory subsystems, and high-speed interfaces.
• Mentor senior engineers and technical leads, improve design and verification methodologies, and resolve complex issues with internal and external IP, EDA, and foundry partners.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, plus 15+ years of experience in semiconductor, ASIC, SoC, or FPGA product development.
• Experience defining and delivering complex silicon architectures from concept through production, including architecture, microarchitecture, RTL design, verification, integration, and post-silicon validation.
• Deep expertise in one or more of on-chip networks, coherent or non-coherent interconnect, memory hierarchy, cache coherency, high-performance networking datapaths, packet processing, or infrastructure-class SoC design.
• Strong understanding of tradeoffs involving bandwidth, latency, congestion, throughput, power, area, timing, and reliability.
• Experience across the silicon development lifecycle with design, verification, emulation, physical design, DFT, firmware/software, and post-silicon teams.
• Proven technical leadership in cross-functional decisions, ambiguous problem resolution, and influencing teams without direct management authority.

Nice to have

• Master’s degree or PhD in a related technical field.
• Experience delivering advanced-node, high-complexity SoCs or ASICs for networking, cloud, AI/ML, communications, storage, security, or data-center infrastructure applications.
• Experience with Network-on-Chip or fabric architecture, including topology, routing, arbitration, quality of service, traffic management, credit-based flow control, and performance analysis.
• Experience with memory systems, cache hierarchy, coherency protocols, HBM/DDR integration, or high-bandwidth data movement.
• Working knowledge of SystemVerilog, simulation, formal verification, emulation, equivalence checking, synthesis, static timing, and implementation flows.
• Experience with architecture modeling, performance analysis, Python automation, AI-assisted engineering workflows, programmable logic devices, heterogeneous SoC platforms, or hard and soft IP integration.
• Technical innovation demonstrated through patents, publications, major product contributions, or industry leadership.

Culture & Benefits

• Regular full-time employment in Shift 1 in the United States.
• Work spans architecture, RTL design, verification, emulation, physical design, software, manufacturing, and post-silicon teams.
• Incentive opportunities reward individual and company performance.
• Applicants must be eligible for any required U.S. export authorizations.