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2 дня назад

Technical Lead Digital Design Engineer (ASIC)

160 000 - 200 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Technical Lead Digital Design Engineer (ASIC): Designing and implementing complex digital blocks for high-performance AI connectivity solutions from micro-architecture through silicon bring-up with an accent on RTL implementation, verification, timing closure, and DFT. Focus on developing high-speed SoC designs, integrating IP and protocols, automating ASIC methodologies, and delivering production-quality silicon.

Location: San Jose, California, United States

Base salary: $160,000–$200,000 USD annually.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and software for CXL, Ethernet, NVLink, PCIe, and UALink systems.

What you will do

  • Own RTL implementation of complex digital designs from micro-architecture through sign-off.
  • Contribute to next-generation high-performance connectivity solutions and take designs through silicon bring-up.
  • Collaborate with verification teams on test plans and debug issues.
  • Support timing closure and implement Design-for-Test features.
  • Develop scripting and automation to improve ASIC methodologies and design infrastructure.
  • Work cross-functionally with verification, physical design, and DFT teams while being accountable for design quality and success.

Requirements

  • Bachelor’s degree in electrical engineering or equivalent.
  • 5+ years of experience developing SoC or silicon products in server, storage, and/or networking markets.
  • Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence.
  • Experience delivering high-quality digital designs from definition to production, including high-speed design in advanced technology nodes.
  • Understanding of functional and formal verification at block and chip level, clocking, CDC, RDC, and static-timing analysis.
  • Proficiency with high-speed protocols such as PCIe, Ethernet, DDR, or similar, plus IP development and integration experience.
  • Expertise in design methodology, CAD automation, or design infrastructure; proven SystemVerilog and Python expertise in a production environment.
  • Familiarity with Synopsys and/or Cadence digital design flows and basic understanding of UVM-based verification methodologies.
  • Ability to learn, balance multiple priorities, adapt to changing requirements, communicate effectively, collaborate with global teams, and work independently on high-quality designs.

Nice to have

  • Experience with embedded firmware development or standard embedded processor subsystems such as RISC-V or Arm.
  • Knowledge of Design-for-Test in a production environment.

Culture & Benefits

  • Fast-paced, collaborative environment focused on creativity, innovation, and diverse perspectives.
  • Work with global cross-functional teams on high-performance connectivity products.
  • hirify.global encourages applications from people with diverse backgrounds and experiences, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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