Principal PCS/PMA RTL Design Engineer

Location: Onsite in San Jose, California, United States

Salary: $185,000–$240,000 per year, depending on experience, level, and business need; discretionary bonus, incentives, and benefits may apply.

Company

hirify.global provides rack-scale AI infrastructure through connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies with its COSMOS software suite.

What you will do

• Develop synthesizable Verilog/SystemVerilog RTL for PCS and PMA blocks supporting Ethernet, PCIe, UCIe, UALink, and related protocols.
• Implement encoding and decoding, scrambling, alignment, lane deskew and bonding, gearboxes, elastic buffers, rate adaptation, FEC, error counters, and status logic.
• Design SerDes and PHY interfaces, CDR and equalization controls, link training, calibration, adaptation, loopback, PRBS, and BIST features.
• Translate architectural specifications into reusable, configurable datapaths, control logic, state machines, register interfaces, and protocol logic.
• Collaborate on simulation, UVM verification, assertions, coverage, lint, CDC/RDC, synthesis, STA, timing closure, power optimization, DFT, ECOs, and implementation signoff.
• Support tapeout, subsystem integration, silicon and link bring-up, interoperability testing, post-silicon debug, and failure analysis with cross-functional teams.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field; a master’s degree is preferred.
• 3+ years of relevant digital ASIC, SoC, or RTL design experience, or equivalent academic and industry experience.
• Hands-on Verilog or SystemVerilog RTL development experience.
• Understanding of combinational and sequential logic, clocks, resets, state machines, datapaths, FIFOs, and interfaces.
• Working knowledge of at least one high-speed serial protocol at the PCS/PHY layer, including Ethernet, PCIe, UCIe, UALink, CXL, or similar.
• Experience with RTL simulation, debugging, synthesis, basic timing analysis, and ASIC design flows.
• Familiarity with collaboration across design and verification teams and strong communication skills.
• Ability and willingness to work onsite in San Jose, California.

Nice to have

• Direct PCS, PMA, or PHY digital logic experience for Ethernet, PCIe, UCIe, UALink, CXL, or similar standards.
• Experience with PAM4, RS-FEC/KP4, FLIT-mode FEC/CRC, lane deskew and alignment, link training, and equalization control.
• Familiarity with PIPE, relevant IEEE 802.3 clauses, PCIe LTSSM, UCIe link training, and sideband protocols.
• Experience with multi-lane, multi-rate SerDes datapaths and clocking architectures.
• Experience with interconnect, networking, or data-center ASICs, including retimers, switches, NICs, DPUs, SmartNICs, or NoCs.
• Experience with Cadence or Synopsys synthesis, implementation, STA, lint, CDC/RDC, DFT, scan, GLS, LEC, UPF, formal verification, UVM, assertions, and functional coverage.
• Scripting experience with Python, Tcl, Perl, Shell, or similar languages.
• Exposure to advanced-node CMOS design, tapeout, silicon bring-up, post-silicon validation, BER measurements, lab debug, and physical-design challenges.

Culture & Benefits

• Collaborative work with architects, design verification, SerDes/analog, physical design, DFT, firmware, systems, packaging, and validation teams.
• Products support next-generation AI and cloud infrastructure through high-performance connectivity and networking ASICs.
• Benefits, incentives, and discretionary bonus eligibility may be available.
• The company encourages applications from people with diverse backgrounds and experiences.