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У роли понятный фокус на проектировании FPGA и серьезные технические задачи, но работа только на месте в США ограничивает доступность вакансии, а диапазон оплаты не указан.
Только офис в США
Понятные задачи
Известный производитель FPGA
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Текст:
Hirify AI/Оригинал
TL;DR
Sr. Staff Design Engineer (FPGA): Developing and validating complex FPGA and SoC systems, including DDR memory controller soft IPs, embedded systems, and high-speed interface subsystems with an accent on RTL design, verification, and performance optimization. Focus on architecting soft IP, achieving timing closure, integrating hardened PHYs, evaluating RISC-V systems, and leading customer-oriented hardware validation.
Location: San Jose, CA, United States; satisfactory proof of the right to work in the United States is required.
Base pay range: $0.00. Variable or incentive compensation and/or equity may also apply.
Company
hirify.global develops programmable logic solutions, including FPGA, CPLD, and programmable power management devices, for global customers.
What you will do
Design and verify RTL for complex FPGA and SoC systems from concept through board-level validation.
Architect and develop DDR memory controller soft IPs, optimizing latency, size, and frequency.
Build embedded systems in Lattice FPGAs, including microprocessor designs and embedded software.
Integrate IPs and third-party hardened PHYs into FPGA software flows and complete end-to-end implementations.
Lead technical coordination with software, applications, customers, and other stakeholders to resolve issues and drive enhancements.
Requirements
Bachelor’s degree in Electronics Engineering, Applied Physics, or a related field.
At least 8 years of experience as a Design Engineer or in a related field.
Experience with FPGA and SoC ASIC development and IP for FPGA and ASIC products.
Experience in FPGA RTL design, logic verification, debugging, and timing closure.
Experience with DDR protocols, including DDR3, DDR4, LPDDR4, or DDR5.
Experience with high-speed interface subsystems and protocols such as PCIe, Ethernet, and MIPI.
Experience with peripheral IPs including UART, SPI, I2C, and I3C.
Experience with hardware validation and hardware interoperability testing.
Culture & Benefits
Results-oriented, team-first environment with cross-functional collaboration.
Comprehensive benefits may include healthcare, retirement plans, and paid time off.
The role may include variable or incentive compensation and/or equity.
Successful background and reference checks are required.
Lattice is an E-Verify employer; new hires must complete Form I-9 employment eligibility verification.
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