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1 день назад

Principal Digital Design Engineer (ASIC)

185 000 - 230 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Principal Digital Design Engineer (ASIC): Developing front-end circuit designs for high-performance network controllers with an accent on micro-architecture, RTL, synthesis, IP integration, and block-level verification. Focus on owning complex ASIC designs from architecture through GDS, implementing high-speed protocols, closing timing, and debugging silicon bring-up.

Location: San Jose, California, United States; other location: California. US work authorization and immediate availability are required.

Base salary: $185,000–$230,000 USD annually.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and the COSMOS software suite.

What you will do

  • Develop micro-architecture and front-end circuit designs for high-performance network controllers.
  • Implement RTL, synthesis, IP integration, simulations, timing closure, GLS, and DFT.
  • Own complex full-chip or block-level designs from architecture through GDS and production.
  • Work with high-speed PCIe, UALink, Esun, and Ethernet communication protocols.
  • Support silicon bring-up and debug.
  • Prioritize multiple tasks, prepare for customer meetings, and work independently with minimal supervision.

Requirements

  • Bachelor’s degree in Electrical Engineering; a Master’s degree is preferred.
  • More than 8 years of experience supporting or developing complex SoC or silicon products for switch ASIC, networking, server, or storage applications.
  • Thorough hands-on knowledge of high-speed protocols including PCIe, UALink, Esun, and Ethernet.
  • Proven front-end design expertise covering architecture, RTL, simulations, synthesis, timing closure, GLS, and DFT.
  • Experience owning multiple complex designs from architecture to GDS and production.
  • Experience with Synopsys and/or Cadence digital design tools and flows.
  • Knowledge of design for test, including stuck-at and transition scan test insertion.
  • Familiarity with UVM-based design verification.
  • Silicon bring-up and debugging expertise.
  • Experience with small-geometry CMOS at 28nm or below.
  • Professional attitude, ability to prioritize dynamically, entrepreneurial and open-minded behavior, and a can-do attitude.

Nice to have

  • Firmware development in C and scripting with Python or equivalent programming languages.
  • Experience developing or supporting PCIe or Ethernet switch products.
  • Master’s degree in Electrical Engineering.

Culture & Benefits

  • Base salary is determined by location, experience, and compensation for similar positions.
  • Creativity and innovation are supported through diverse ideas, backgrounds, and experiences.
  • Applicants from diverse backgrounds, including veterans, parents, people with disabilities, LGBTQ+ and non-binary people, and people of color, are encouraged to apply.

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