Director of Physical Design (AI)

Location: San Francisco County, California, United States

Salary: $320,000

Company

hirify.global is partnering with a startup developing a 3D-memory-integrated AI accelerator platform.

What you will do

• Lead full-chip and complex subsystem physical design from netlist ingestion through GDSII signoff for AI accelerators and 3D-memory PHY hard IP.
• Own floorplanning, clock-tree synthesis, routing, timing closure, physical verification, and PD flow development using Innovus and Genus.
• Plan team execution, coordinate external design-service partners, allocate resources, and lead milestone, quality, readiness, and tapeout reviews.
• Collaborate with SoC, DFT, packaging, and foundry teams on 3D-memory, chiplet connectivity, and power-integrity challenges.
• Develop power-grid strategies and perform IR-drop and electromigration analysis using Cadence Voltus or ANSYS RedHawk, including TSV-based power-delivery constraints.
• Drive DFT implementation and DRC/LVS/ERC signoff, including scan routing, BIST, JTAG, boundary scan, test-mode power constraints, and clean tapeout.

Requirements

• B.E. or M.S. in Electrical Engineering, VLSI, or a related discipline.
• 15–20 years of ASIC/SoC physical-design experience with successful silicon tapeouts.
• Expert proficiency with physical-design tools, flows, and advanced 3nm, 5nm, or 7nm process nodes.
• Mastery of CTS, timing- and congestion-aware routing, SI-aware signoff, and low-power and DFT design flows.
• Experience implementing NoC, Fabric, or AXI interconnects and placing and routing high-performance on-chip networks.
• Experience with DFT-aware physical design, including scan-chain routing, BIST controller placement, JTAG/boundary-scan integration, and test-mode physical constraints.
• Experience with UPF-based multi-voltage domains, power gating, retention-flop placement, level shifters, and isolation cells.
• Proven multiple successful SoC productizations from physical design through post-silicon qualification and production release.
• Strong leadership, communication, and project-management skills in fast-paced environments.

Culture & Benefits

• High-impact technical leadership role in a fast-paced startup environment.
• Responsibility for physical-design methodology, flow development, execution, and VLSI trade-offs across power, performance, area, schedule, and design quality.