Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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В заголовке указана роль Technical Program Manager, но описание посвящено практической работе старшего инженера цифрового проектирования. Из-за этого непонятно, на какую позицию фактически набирают.
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Несовпадение ролиОшибки в текстеПередовые разработкиАктуальные технологииВлияние на продукт
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Текст:
Hirify AI/Оригинал
TL;DR
Technical Program Manager (AI): Driving invention, prototyping, and validation of core components for an energy-efficient AI computing platform with an accent on SoC architecture, RTL implementation, and ASIC design flow execution. Focus on defining digital micro-architecture, integrating third-party IP, meeting power-performance-area targets, and resolving synthesis, timing, CDC, and verification challenges.
Location: Mountain View, California, with complimentary meals in the Palo Alto office.
Company
hirify.global is developing a new computing foundation for AI by exploiting semiconductor physics to achieve significantly higher energy efficiency.
What you will do
Define micro-architecture and integrate digital blocks, including CPU, memory subsystems, interfaces, and third-party IP, into the SoC fabric.
Lead hands-on Verilog RTL design and debugging for complex, timing-critical SoC blocks and digital interfaces while meeting power, performance, and area targets.
Support block-level design verification by contributing to verification plans, developing verification infrastructure, and debugging simulation failures.
Coordinate hand-off between design and physical implementation teams through synthesis and timing closure.
Mentor junior digital design engineers and help establish design methodologies, code-review practices, quality processes, and early-stage tapeout infrastructure.
Requirements
B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
8+ years of industry experience in digital ASIC/SoC design.
Expertise in Verilog RTL coding and digital design fundamentals.
Familiarity with standard EDA tools for simulation, synthesis, linting, and CDC analysis.
Understanding of the full ASIC design flow from specification through tape-out.
Excellent written and verbal communication skills.
Ability to lead junior engineers toward team goals and support their skill development.
Nice to have
Experience with synchronous and asynchronous logic, state machines, and bus protocols.
Experience developing scripts or tooling for design automation.
Experience optimizing designs for performance, power, or area.
Experience with modern design methods, including generative AI code development platforms.
Experience with analog mixed-signal technology and interfaces.
Culture & Benefits
Work on complex, unsolved problems spanning AI, physics, and computer architecture.
Foundational-team ownership and the opportunity to influence the company's future direction.
Health benefits, 401(k) matching, and unlimited paid time off.
Complimentary meals at the Palo Alto office.
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