VLSI Physical Design Lead Engineer

Location: Hybrid, with an average requirement of two days per week from an HPE office in Ft. Collins, Colorado; Bloomington, Minnesota; or Chippewa Falls, Wisconsin, United States.

Salary: Base annual salary of USD 168,000–319,000 in Colorado or USD 159,500–367,000 in Minnesota and Wisconsin. Variable incentives may also be offered.

Company

hirify.global is a global edge-to-cloud company developing infrastructure and solutions for data and applications.

What you will do

• Develop organization-wide VLSI design architectures, methodologies, and implementation flows across multiple platforms and organizations.
• Design, analyze, evaluate, and optimize complex VLSI components, integrated circuits, and high-performance ASIC implementations.
• Review designs and projects for compliance with technology and development standards, influencing strategic technical and cost decisions.
• Provide technical leadership and accountability for multiple project teams, engineers, outsourced partners, and industry standards initiatives.
• Identify emerging VLSI technologies and new project opportunities while contributing to product features and industry standards.
• Mentor engineers, support technical-leader selection, and share VLSI design and development expertise across the organization.

Requirements

• Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or an equivalent field.
• Typically 10+ years of experience in VLSI, physical design, ASIC implementation, or related electronic design fields.
• Leadership experience and mastery of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
• Experience with static timing analysis and signoff, timing constraints and validation, synthesis and netlist quality analysis, formal verification, floorplanning, chip partitioning, and ECO implementation.
• Experience with industry-standard EDA tools such as Synopsys Fusion Compiler, Design Compiler, PrimeTime, or Formality, and/or Cadence RTL Compiler, Genus, or LEC.
• Experience with clock, I/O, test, specialized timing-closure challenges, hierarchical timing analysis, and full-chip timing closure.
• Experience developing ASIC implementation flows, automation, and design methodologies for advanced process technologies and complex, high-performance ASIC designs.
• Mastery of programming and scripting, a hardware description language, EDA, and/or FPGA tools; coursework in VLSI design or VLSI concepts.
• Excellent analytical, problem-solving, communication, independent-working, collaboration, technical-leadership, mentoring, and cross-functional decision-making skills; mastery in English and the local language.
• History of innovation and technical leadership, including multiple patents, publications, or technical presentations in VLSI or electronic/hardware component design and tools.

Nice to have

• Experience using AI tools and methodologies to run design experiments, learn new information, and optimize flows.
• Publications, patents, or other demonstrated contributions in ASIC, VLSI, physical design, or electronic design automation.

Culture & Benefits

• Hybrid work model with regular office presence.
• Health and wellbeing benefits supporting physical, financial, and emotional wellbeing.
• Personal and professional development programs supporting career growth and technical expertise.
• Inclusive workplace focused on varied backgrounds, flexibility, collaboration, and innovation.
• Applications are encouraged from qualified individuals with disabilities, with accommodation support available during the application or interview process.