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Hirify AI/Оригинал
TL;DR
Director of Physical Design (AI/MCU): Leading physical implementation for next-generation ultra-low-power MCU products with an accent on PPA optimization, low-power architecture, and robust silicon delivery. Focus on scaling a global physical design organization, driving floorplanning, CTS, place and route, timing closure, verification, EM/IR sign-off, and tape-out readiness.
Location: On-site 5 days a week in NW Austin, Texas, United States. Candidates must be currently authorized to work in the United States for any employer.
Company
hirify.global develops ultra-low-power semiconductor solutions for AI edge, wearable, medical device, IoT, and embedded applications.
What you will do
Lead the physical design strategy and roadmap for next-generation ultra-low-power MCU product lines.
Build, mentor, and manage a global physical design organization spanning methodology, physical implementation, and sign-off.
Oversee floorplanning, power planning, clock tree synthesis, place and route, timing closure, physical verification, EM/IR and reliability sign-off, and power analysis.
Drive PPA optimization, low-power implementation, design-flow automation, sign-off quality, and the use of AI tools.
Partner with architecture, RTL, analog/mixed-signal, verification, product engineering, operations, and foundries on SoC integration, manufacturability, yield, PDKs, and design rules.
Own schedules, resource planning, risk management, tape-out readiness, first-silicon success, and post-silicon debug.
Requirements
Bachelor’s or Master’s degree in electrical engineering, computer engineering, or a related field.
15+ years of physical design experience for complex SoCs, including at least 5 years in leadership roles.
Proven delivery of multiple chips to production.
Deep expertise in low-power design techniques, including UPF, clock gating, multi-Vt, power gating, DVFS, and retention.
Experience with Synopsys, Cadence, and Mentor physical design tools.
Experience with advanced process nodes from 40nm through 22nm, 12nm, and below.
Strong understanding of MCU architectures and embedded-system constraints.
Excellent communication, leadership, and cross-functional collaboration skills.
Current authorization to work in the United States for any employer.
Nice to have
Experience with mixed-signal SoCs and analog IP integration.
Background in high-volume consumer or industrial MCU products.
Familiarity with security-focused or safety-certified MCU designs, such as ISO 26262.
Experience building and scaling distributed engineering teams.
Culture & Benefits
On-site work in NW Austin five days per week.
Cross-functional collaboration across design, research, development, production, marketing, sales, and operations.
Work on complex semiconductor products focused on energy efficiency and AI edge applications.
Company values include innovation, collaboration, focus, learning, and achievement.
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