Head of ASIC Engineering (AI)

Location: On-site in Palo Alto, California, United States

Company

hirify.global is a frontier AI lab developing custom silicon with frontier labs, clouds, physical AI companies, and advanced fabs.

What you will do

• Own ASIC methodology and end-to-end delivery of ambitious AI compute silicon.
• Lead programs from microarchitecture and RTL through verification, physical design, signoff, and tapeout.
• Build faster AI-native chip-development flows using automation, intelligent agents, and data-driven feedback loops.
• Accelerate design iteration, verification, closure, and engineering productivity.
• Lead and develop a world-class silicon engineering team while setting a high bar for PPA and silicon quality.
• Drive consequential technical and execution decisions and resolve complex cross-functional engineering problems.

Requirements

• Directly lead multiple complex, production-volume ASIC or SoC programs with repeated tapeout success, ideally at advanced process nodes.
• Deep expertise across RTL, functional verification, synthesis, timing closure, physical implementation, DFT, signoff, and silicon bring-up.
• Track record of transforming design flows through automation, ML/AI-assisted EDA, verification productivity, or scalable engineering infrastructure.
• Demonstrated ability to deliver demanding programs with strong first-silicon outcomes and disciplined engineering tradeoffs.
• Record of recruiting, developing, and leading world-class silicon engineers and technical leaders.
• Hands-on technical leadership and the ability to resolve difficult cross-functional engineering problems personally while building scalable processes.

Culture & Benefits

• Full-time, on-site role in Palo Alto.
• Competitive compensation and meaningful equity.
• Ownership of critical silicon programs and the opportunity to build an ASIC organization at the frontier of computing.