VLSI Physical Design Engineer (ASIC)

Location: Hybrid, with an average requirement of 2 days per week in an HPE office in Ft. Collins, Colorado; Bloomington, Minnesota; or Chippewa Falls, Wisconsin.

Salary: Annual base salary of USD 115,000–218,000 in Colorado and USD 109,000–251,000 in Minnesota and Wisconsin. Variable incentives may also be offered.

Company

hirify.global is an edge-to-cloud technology company developing solutions for connecting, protecting, analyzing, and acting on data and applications.

What you will do

• Perform static timing analysis for hierarchical partitions and full-chip designs, maintaining timing constraints and budgets.
• Drive timing closure across setup, hold, clock, I/O, and test timing while resolving critical paths and meeting performance, power, and area objectives.
• Perform synthesis, netlist quality checks, formal verification, chip partitioning, floorplanning, physical implementation, and ECO management.
• Develop automation and methodology improvements for synthesis, timing analysis, formal verification, physical design, and signoff, including AI-assisted methods.
• Partner with architecture, design, physical implementation, DFT, signal integrity, external design partners, and other engineering teams.
• Provide technical guidance to less-experienced engineers and support compliance with ASIC technology, methodology, and development standards.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or an equivalent field.
• 1–6 years of experience in VLSI design, verification, or implementation.
• Strong knowledge of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
• Experience with one or more of static timing analysis and signoff, timing constraints and validation, synthesis and netlist quality analysis, formal verification, floorplanning and chip partitioning, or ECO implementation.
• Experience with industry-standard EDA tools such as Synopsys Fusion Compiler, Design Compiler, PrimeTime, Formality, Cadence RTL Compiler, Genus, or LEC.
• Strong analytical, problem-solving, written, and verbal communication skills.
• Experience designing VLSI components, integrated circuitry, architectures, and algorithms.
• Ability to work independently and collaboratively across multiple engineering disciplines.
• Knowledge of programming and scripting, hardware description languages, EDA, and/or FPGA tools; coursework in VLSI design or VLSI concepts.
• Mastery of English and the local language required.

Culture & Benefits

• Hybrid work with regular office collaboration.
• Health and wellbeing benefits for employees and their families.
• Personal and professional development programs supporting career growth and expertise.
• Inclusive workplace that values varied backgrounds and provides flexibility to manage work and personal needs.
• Estimated application-period closure: February 1, 2027.